Open Menu / drivers / gpu / drm / i915 / display / intel_cmtg_regs.h 
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/* SPDX-License-Identifier: MIT */
/*
 * Copyright (C) 2025 Intel Corporation
 */

#ifndef __INTEL_CMTG_REGS_H__
#define __INTEL_CMTG_REGS_H__

#include "intel_display_reg_defs.h"

#define CMTG_CLK_SEL			_MMIO(0x46160)
#define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
#define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
#define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
#define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)

#define _TRANS_CMTG_CTL_A		0x6fa88
#define _TRANS_CMTG_CTL_B		0x6fb88
#define TRANS_CMTG_CTL(trans)		_MMIO_TRANS((trans), \
						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
#define  CMTG_ENABLE			REG_BIT(31)
#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
#define  CMTG_STATE			REG_BIT(23)

#define _CMTG_HW_GB_A				0x6fa8c
#define _CMTG_HW_GB_B				0x6fb8c
#define CMTG_HW_GB(trans)			_MMIO_TRANS((trans), \
							    _CMTG_HW_GB_A, _CMTG_HW_GB_B)
#define CMTG_HW_GB_BREAKEVEN_MASK		REG_GENMASK(11, 0)
#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)

#define _CMTG_SCANLINE_GB1_A		0x456A0
#define _CMTG_SCANLINE_GB1_B		0x456C0
#define CMTG_SCANLINE_GB1(trans)	_MMIO_TRANS((trans), \
						    _CMTG_SCANLINE_GB1_A, _CMTG_SCANLINE_GB1_B)
#define  CMTG_HW_GB_ENABLE		REG_BIT(31)

#endif /* __INTEL_CMTG_REGS_H__ */