// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
* Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
*/
#include <dt-bindings/clock/spacemit,k3-clocks.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/spacemit,k3-resets.h>
#include <dt-bindings/phy/phy.h>
#include "k3-pdma.h"
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "SpacemiT K3";
compatible = "spacemit,k3";
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <24000000>;
cpu_0: cpu@0 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache0>;
mmu-type = "riscv,sv39";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_1: cpu@1 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <1>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache0>;
mmu-type = "riscv,sv39";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_2: cpu@2 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <2>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache0>;
mmu-type = "riscv,sv39";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_3: cpu@3 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <3>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache0>;
mmu-type = "riscv,sv39";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_4: cpu@4 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <4>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache1>;
mmu-type = "riscv,sv39";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_5: cpu@5 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <5>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache1>;
mmu-type = "riscv,sv39";
cpu5_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_6: cpu@6 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <6>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache1>;
mmu-type = "riscv,sv39";
cpu6_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu_7: cpu@7 {
compatible = "spacemit,x100", "riscv";
device_type = "cpu";
reg = <7>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
"sha", "shcounterenw", "shgatpa", "shtvala",
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
"smstateen", "ssaia", "ssccptr", "sscofpmf",
"sscounterenw", "ssnpm", "ssstateen", "sstc",
"sstvala", "sstvecd", "ssu64xl", "svade",
"svinval", "svnapot", "svpbmt", "za64rs",
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <256>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache1>;
mmu-type = "riscv,sv39";
cpu7_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
l2_cache0: cache-controller-0 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <4194304>;
cache-sets = <4096>;
cache-unified;
};
l2_cache1: cache-controller-1 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <4194304>;
cache-sets = <4096>;
cache-unified;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_0>;
};
core1 {
cpu = <&cpu_1>;
};
core2 {
cpu = <&cpu_2>;
};
core3 {
cpu = <&cpu_3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_4>;
};
core1 {
cpu = <&cpu_5>;
};
core2 {
cpu = <&cpu_6>;
};
core3 {
cpu = <&cpu_7>;
};
};
};
};
clocks {
vctcxo_1m: clock-1m {
compatible = "fixed-clock";
clock-frequency = <1000000>;
clock-output-names = "vctcxo_1m";
#clock-cells = <0>;
};
vctcxo_24m: clock-24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "vctcxo_24m";
#clock-cells = <0>;
};
vctcxo_3m: clock-3m {
compatible = "fixed-clock";
clock-frequency = <3000000>;
clock-output-names = "vctcxo_3m";
#clock-cells = <0>;
};
osc_32k: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc_32k";
#clock-cells = <0>;
};
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&saplic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
usb3d: usb@81a00000 {
compatible = "spacemit,k3-dwc3";
reg = <0x0 0x81a00000 0x0 0x10000>;
interrupts = <149 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&saplic>;
clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>;
clock-names = "usbdrd30";
resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>,
<&syscon_apmu RESET_APMU_USB3_D_VCC>,
<&syscon_apmu RESET_APMU_USB3_D_PHY>;
reset-names = "ahb", "vcc", "phy";
phys = <&usb3d_u2phy>,
<&combophy 4 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi";
snps,dis_enblslpm_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
dr_mode = "host";
status = "disabled";
};
usb3d_u2phy: phy@81b00000 {
compatible = "spacemit,k3-usb2-phy";
reg = <0x0 0x81b00000 0x0 0x200>;
clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>;
#phy-cells = <0>;
status = "disabled";
};
combophy: phy@81d00000 {
compatible = "spacemit,k3-combo-phy";
reg = <0x0 0x81d00000 0x0 0x600000>;
#phy-cells = <2>;
spacemit,apb-spare = <&pll>;
status = "disabled";
};
usb2_host: usb@c0a00000 {
compatible = "spacemit,k3-dwc3";
reg = <0x0 0xc0a00000 0x0 0x10000>;
clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
clock-names = "usbdrd30";
resets = <&syscon_apmu RESET_APMU_USB2_AHB>,
<&syscon_apmu RESET_APMU_USB2_VCC>,
<&syscon_apmu RESET_APMU_USB2_PHY>;
reset-names = "ahb", "vcc", "phy";
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&saplic>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
phy_type = "utmi";
snps,dis_enblslpm_quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
dr_mode = "host";
maximum-speed = "high-speed";
status = "disabled";
};
usb2_phy: phy@c0a20000 {
compatible = "spacemit,k3-usb2-phy";
reg = <0x0 0xc0a20000 0x0 0x200>;
clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
#phy-cells = <0>;
status = "disabled";
};
eth0: ethernet@cac80000 {
compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a";
reg = <0x0 0xcac80000 0x0 0x2000>;
clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>,
<&syscon_apmu CLK_APMU_EMAC0_1588>,
<&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>;
clock-names = "stmmaceth", "ptp_ref", "tx";
interrupts = <131 IRQ_TYPE_LEVEL_HIGH>,
<276 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
resets = <&syscon_apmu RESET_APMU_EMAC0>;
reset-names = "stmmaceth";
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
snps,aal;
snps,tso;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,force_sf_dma_mode;
snps,axi-config = <&gmac0_axi_setup>;
spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>;
status = "disabled";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
gmac0_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
/* max axi burst len is 256 */
snps,blen = <256 128 64 32 16 0 0>;
};
};
eth1: ethernet@cac82000 {
compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a";
reg = <0x0 0xcac82000 0x0 0x2000>;
clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>,
<&syscon_apmu CLK_APMU_EMAC1_1588>,
<&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>;
clock-names = "stmmaceth", "ptp_ref", "tx";
interrupts = <133 IRQ_TYPE_LEVEL_HIGH>,
<277 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
resets = <&syscon_apmu RESET_APMU_EMAC1>;
reset-names = "stmmaceth";
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
snps,aal;
snps,tso;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,force_sf_dma_mode;
snps,axi-config = <&gmac1_axi_setup>;
spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>;
status = "disabled";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
gmac1_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
/* max axi burst len is 256 */
snps,blen = <256 128 64 32 16 0 0>;
};
};
eth2: ethernet@cac8e000 {
compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a";
reg = <0x0 0xcac8e000 0x0 0x2000>;
clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>,
<&syscon_apmu CLK_APMU_EMAC2_1588>,
<&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>;
clock-names = "stmmaceth", "ptp_ref", "tx";
interrupts = <130 IRQ_TYPE_LEVEL_HIGH>,
<278 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
resets = <&syscon_apmu RESET_APMU_EMAC2>;
reset-names = "stmmaceth";
rx-fifo-depth = <4096>;
tx-fifo-depth = <4096>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
snps,aal;
snps,tso;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,force_sf_dma_mode;
snps,axi-config = <&gmac2_axi_setup>;
spacemit,apmu = <&syscon_apmu 0x248 0x24c>;
status = "disabled";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
gmac2_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
/* max axi burst len is 256 */
snps,blen = <256 128 64 32 16 0 0>;
};
};
pdma: dma-controller@d4000000 {
compatible = "spacemit,k3-pdma";
reg = <0x0 0xd4000000 0x0 0x4000>;
clocks = <&syscon_apmu CLK_APMU_DMA>;
resets = <&syscon_apmu RESET_APMU_DMA>;
interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <1>;
status = "disabled";
};
i2c0: i2c@d4010800 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd4010800 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI0>,
<&syscon_apbc CLK_APBC_TWSI0_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI0>;
status = "disabled";
};
i2c1: i2c@d4011000 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd4011000 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI1>,
<&syscon_apbc CLK_APBC_TWSI1_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI1>;
status = "disabled";
};
i2c2: i2c@d4012000 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd4012000 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI2>,
<&syscon_apbc CLK_APBC_TWSI2_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI2>;
status = "disabled";
};
i2c4: i2c@d4012800 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd4012800 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI4>,
<&syscon_apbc CLK_APBC_TWSI4_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI4>;
status = "disabled";
};
i2c5: i2c@d4013800 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd4013800 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI5>,
<&syscon_apbc CLK_APBC_TWSI5_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI5>;
status = "disabled";
};
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k3-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@d4017000 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART0>,
<&syscon_apbc CLK_APBC_UART0_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART0>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart2: serial@d4017100 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017100 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART2>,
<&syscon_apbc CLK_APBC_UART2_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART2>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart3: serial@d4017200 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017200 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART3>,
<&syscon_apbc CLK_APBC_UART3_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART3>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@d4017300 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017300 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART4>,
<&syscon_apbc CLK_APBC_UART4_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART4>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart5: serial@d4017400 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017400 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART5>,
<&syscon_apbc CLK_APBC_UART5_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART5>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart6: serial@d4017500 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017500 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART6>,
<&syscon_apbc CLK_APBC_UART6_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART6>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart7: serial@d4017600 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017600 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART7>,
<&syscon_apbc CLK_APBC_UART7_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART7>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart8: serial@d4017700 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017700 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART8>,
<&syscon_apbc CLK_APBC_UART8_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART8>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart9: serial@d4017800 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd4017800 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART9>,
<&syscon_apbc CLK_APBC_UART9_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART9>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c6: i2c@d4018800 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd4018800 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI6>,
<&syscon_apbc CLK_APBC_TWSI6_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI6>;
status = "disabled";
};
gpio: gpio@d4019000 {
compatible = "spacemit,k3-gpio";
reg = <0x0 0xd4019000 0x0 0x100>;
clocks = <&syscon_apbc CLK_APBC_GPIO>,
<&syscon_apbc CLK_APBC_GPIO_BUS>;
clock-names = "core", "bus";
gpio-controller;
#gpio-cells = <3>;
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&saplic>;
interrupt-controller;
#interrupt-cells = <3>;
gpio-ranges = <&pinctrl 0 0 0 32>,
<&pinctrl 1 0 32 32>,
<&pinctrl 2 0 64 32>,
<&pinctrl 3 0 96 32>;
};
i2c8: i2c@d401d800 {
compatible = "spacemit,k3-i2c", "spacemit,k1-i2c";
reg = <0x0 0xd401d800 0x0 0x38>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon_apbc CLK_APBC_TWSI8>,
<&syscon_apbc CLK_APBC_TWSI8_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_APBC_TWSI8>;
status = "disabled";
};
pwm0: pwm@d401a000 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401a000 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM0>,
<&syscon_apbc CLK_APBC_PWM0_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM0>;
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@d401a400 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401a400 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM1>,
<&syscon_apbc CLK_APBC_PWM1_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM1>;
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@d401a800 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401a800 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM2>,
<&syscon_apbc CLK_APBC_PWM2_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM2>;
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@d401ac00 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401ac00 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM3>,
<&syscon_apbc CLK_APBC_PWM3_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM3>;
#pwm-cells = <3>;
status = "disabled";
};
pwm4: pwm@d401b000 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401b000 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM4>,
<&syscon_apbc CLK_APBC_PWM4_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM4>;
#pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@d401b400 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401b400 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM5>,
<&syscon_apbc CLK_APBC_PWM5_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM5>;
#pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@d401b800 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401b800 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM6>,
<&syscon_apbc CLK_APBC_PWM6_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM6>;
#pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@d401bc00 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd401bc00 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM7>,
<&syscon_apbc CLK_APBC_PWM7_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM7>;
#pwm-cells = <3>;
status = "disabled";
};
spi3: spi@d401c000 {
compatible = "spacemit,k3-spi", "spacemit,k1-spi";
reg = <0x0 0xd401c000 0x0 0x30>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&syscon_apbc CLK_APBC_SPI3>,
<&syscon_apbc CLK_APBC_SPI3_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_SPI3>;
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma K3_PDMA_SSP3_RX>, <&pdma K3_PDMA_SSP3_TX>;
dma-names = "rx", "tx";
status = "disabled";
};
pwm8: pwm@d4020000 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4020000 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM8>,
<&syscon_apbc CLK_APBC_PWM8_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM8>;
#pwm-cells = <3>;
status = "disabled";
};
pwm9: pwm@d4020400 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4020400 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM9>,
<&syscon_apbc CLK_APBC_PWM9_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM9>;
#pwm-cells = <3>;
status = "disabled";
};
pwm10: pwm@d4020800 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4020800 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM10>,
<&syscon_apbc CLK_APBC_PWM10_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM10>;
#pwm-cells = <3>;
status = "disabled";
};
pwm11: pwm@d4020c00 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4020c00 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM11>,
<&syscon_apbc CLK_APBC_PWM11_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM11>;
#pwm-cells = <3>;
status = "disabled";
};
pwm12: pwm@d4021000 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4021000 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM12>,
<&syscon_apbc CLK_APBC_PWM12_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM12>;
#pwm-cells = <3>;
status = "disabled";
};
pwm13: pwm@d4021400 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4021400 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM13>,
<&syscon_apbc CLK_APBC_PWM13_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM13>;
#pwm-cells = <3>;
status = "disabled";
};
pwm14: pwm@d4021800 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4021800 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM14>,
<&syscon_apbc CLK_APBC_PWM14_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM14>;
#pwm-cells = <3>;
status = "disabled";
};
pwm15: pwm@d4021c00 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4021c00 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM15>,
<&syscon_apbc CLK_APBC_PWM15_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM15>;
#pwm-cells = <3>;
status = "disabled";
};
pwm16: pwm@d4022000 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4022000 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM16>,
<&syscon_apbc CLK_APBC_PWM16_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM16>;
#pwm-cells = <3>;
status = "disabled";
};
pwm17: pwm@d4022400 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4022400 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM17>,
<&syscon_apbc CLK_APBC_PWM17_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM17>;
#pwm-cells = <3>;
status = "disabled";
};
pwm18: pwm@d4022800 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4022800 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM18>,
<&syscon_apbc CLK_APBC_PWM18_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM18>;
#pwm-cells = <3>;
status = "disabled";
};
pwm19: pwm@d4022c00 {
compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm";
reg = <0x0 0xd4022c00 0x0 0x10>;
clocks = <&syscon_apbc CLK_APBC_PWM19>,
<&syscon_apbc CLK_APBC_PWM19_BUS>;
clock-names = "func", "bus";
resets = <&syscon_apbc RESET_APBC_PWM19>;
#pwm-cells = <3>;
status = "disabled";
};
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k3-pinctrl";
reg = <0x0 0xd401e000 0x0 0x1000>;
clocks = <&syscon_apbc CLK_APBC_AIB>,
<&syscon_apbc CLK_APBC_AIB_BUS>;
clock-names = "func", "bus";
spacemit,apbc = <&syscon_apbc>;
};
uart10: serial@d401f000 {
compatible = "spacemit,k3-uart", "intel,xscale-uart";
reg = <0x0 0xd401f000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&syscon_apbc CLK_APBC_UART10>,
<&syscon_apbc CLK_APBC_UART10_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_UART10>;
interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi0: spi@d4040000 {
compatible = "spacemit,k3-spi", "spacemit,k1-spi";
reg = <0x0 0xd4040000 0x0 0x30>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&syscon_apbc CLK_APBC_SPI0>,
<&syscon_apbc CLK_APBC_SPI0_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_SPI0>;
interrupts = <283 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma K3_PDMA_SSP0_RX>, <&pdma K3_PDMA_SSP0_TX>;
dma-names = "rx", "tx";
status = "disabled";
};
spi1: spi@d4040800 {
compatible = "spacemit,k3-spi", "spacemit,k1-spi";
reg = <0x0 0xd4040800 0x0 0x30>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&syscon_apbc CLK_APBC_SPI1>,
<&syscon_apbc CLK_APBC_SPI1_BUS>;
clock-names = "core", "bus";
resets = <&syscon_apbc RESET_APBC_SPI1>;
interrupts = <282 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma K3_PDMA_SSP1_RX>, <&pdma K3_PDMA_SSP1_TX>;
dma-names = "rx", "tx";
status = "disabled";
};
syscon_mpmu: system-controller@d4050000 {
compatible = "spacemit,k3-syscon-mpmu";
reg = <0x0 0xd4050000 0x0 0x10000>;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
pll: clock-controller@d4090000 {
compatible = "spacemit,k3-pll";
reg = <0x0 0xd4090000 0x0 0x10000>;
clocks = <&vctcxo_24m>;
spacemit,mpmu = <&syscon_mpmu>;
#clock-cells = <1>;
};
qspi: spi@d420c000 {
compatible = "spacemit,k3-qspi",
"spacemit,k1-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xd420c000 0x0 0x1000>,
<0x0 0xb8000000 0x0 0xc00000>;
reg-names = "QuadSPI", "QuadSPI-memory";
clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>,
<&syscon_apmu CLK_APMU_QSPI>;
clock-names = "qspi_en", "qspi";
resets = <&syscon_apmu RESET_APMU_QSPI>,
<&syscon_apmu RESET_APMU_QSPI_BUS>;
interrupts = <117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci0: mmc@d4280000 {
compatible = "spacemit,k3-sdhci";
reg = <0x0 0xd4280000 0x0 0x200>;
clocks = <&syscon_apmu CLK_APMU_SDH_AXI>,
<&syscon_apmu CLK_APMU_SDH0>;
clock-names = "core", "io";
resets = <&syscon_apmu RESET_APMU_SDH_AXI>,
<&syscon_apmu RESET_APMU_SDH0>;
reset-names = "axi", "sdh";
interrupts = <99 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
syscon_apmu: system-controller@d4282800 {
compatible = "spacemit,k3-syscon-apmu";
reg = <0x0 0xd4282800 0x0 0x400>;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
syscon_dciu: system-controller@d8440000 {
compatible = "spacemit,k3-syscon-dciu";
reg = <0x0 0xd8440000 0x0 0xc000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
simsic: interrupt-controller@e0400000 {
compatible = "spacemit,k3-imsics", "riscv,imsics";
reg = <0x0 0xe0400000 0x0 0x200000>;
#interrupt-cells = <0>;
#msi-cells = <0>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
<&cpu2_intc 9>, <&cpu3_intc 9>,
<&cpu4_intc 9>, <&cpu5_intc 9>,
<&cpu6_intc 9>, <&cpu7_intc 9>;
msi-controller;
riscv,guest-index-bits = <6>;
riscv,hart-index-bits = <4>;
riscv,num-guest-ids = <511>;
riscv,num-ids = <511>;
};
saplic: interrupt-controller@e0804000 {
compatible = "spacemit,k3-aplic", "riscv,aplic";
reg = <0x0 0xe0804000 0x0 0x4000>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&simsic>;
riscv,num-sources = <512>;
};
clint: timer@e081c000 {
compatible = "spacemit,k3-clint", "sifive,clint0";
reg = <0x0 0xe081c000 0x0 0x4000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>,
<&cpu5_intc 3>, <&cpu5_intc 7>,
<&cpu6_intc 3>, <&cpu6_intc 7>,
<&cpu7_intc 3>, <&cpu7_intc 7>;
};
/* sec_i2c3: 0xf0614000, not available from Linux */
mimsic: interrupt-controller@f1000000 {
compatible = "spacemit,k3-imsics", "riscv,imsics";
reg = <0x0 0xf1000000 0x0 0x10000>;
#interrupt-cells = <0>;
#msi-cells = <0>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
<&cpu2_intc 11>, <&cpu3_intc 11>,
<&cpu4_intc 11>, <&cpu5_intc 11>,
<&cpu6_intc 11>, <&cpu7_intc 11>;
msi-controller;
riscv,guest-index-bits = <6>;
riscv,hart-index-bits = <4>;
riscv,num-guest-ids = <511>;
riscv,num-ids = <511>;
status = "reserved";
};
maplic: interrupt-controller@f1800000 {
compatible = "spacemit,k3-aplic", "riscv,aplic";
reg = <0x0 0xf1800000 0x0 0x4000>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&mimsic>;
riscv,children = <&saplic>;
riscv,delegation = <&saplic 1 512>;
riscv,num-sources = <512>;
status = "reserved";
};
};
};
