// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/clock/qcom,glymur-camcc.h>
#include <dt-bindings/clock/qcom,glymur-dispcc.h>
#include <dt-bindings/clock/qcom,glymur-evacc.h>
#include <dt-bindings/clock/qcom,glymur-gcc.h>
#include <dt-bindings/clock/qcom,glymur-gpucc.h>
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
#include <dt-bindings/clock/qcom,glymur-videocc.h>
#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
#include "glymur-ipcc.h"
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,oryon-2-2";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd0>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,oryon-2-2";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd1>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,oryon-2-2";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd2>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,oryon-2-2";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd3>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,oryon-2-2";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd4>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,oryon-2-2";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd5>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
cpu6: cpu@10000 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10000>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd6>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu7: cpu@10100 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10100>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd7>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu8: cpu@10200 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10200>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd8>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu9: cpu@10300 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10300>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd9>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu10: cpu@10400 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10400>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd10>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu11: cpu@10500 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10500>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd11>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu12: cpu@20000 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20000>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd12>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
#cooling-cells = <2>;
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu13: cpu@20100 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20100>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd13>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
#cooling-cells = <2>;
};
cpu14: cpu@20200 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20200>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd14>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
#cooling-cells = <2>;
};
cpu15: cpu@20300 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20300>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd15>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
#cooling-cells = <2>;
};
cpu16: cpu@20400 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20400>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd16>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
#cooling-cells = <2>;
};
cpu17: cpu@20500 {
device_type = "cpu";
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20500>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd17>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
};
cluster1 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
core2 {
cpu = <&cpu8>;
};
core3 {
cpu = <&cpu9>;
};
core4 {
cpu = <&cpu10>;
};
core5 {
cpu = <&cpu11>;
};
};
cpu_map_cluster2: cluster2 {
core0 {
cpu = <&cpu12>;
};
core1 {
cpu = <&cpu13>;
};
core2 {
cpu = <&cpu14>;
};
core3 {
cpu = <&cpu15>;
};
core4 {
cpu = <&cpu16>;
};
core5 {
cpu = <&cpu17>;
};
};
};
idle-states {
entry-method = "psci";
cpu_c4: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <180>;
exit-latency-us = <320>;
min-residency-us = <1000>;
};
};
domain-idle-states {
cluster_cl5: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <9000>;
};
domain_ss3: domain-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x0200c354>;
entry-latency-us = <2800>;
exit-latency-us = <4400>;
min-residency-us = <10150>;
};
};
};
dummy-sink {
compatible = "arm,coresight-dummy-sink";
in-ports {
port {
eud_in: endpoint {
remote-endpoint = <&swao_rep_out1>;
};
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-glymur", "qcom,scm";
qcom,dload-mode = <&tcsr 0x4000>;
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
scmi {
compatible = "arm,scmi";
mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
mbox-names = "tx", "rx";
shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>;
#address-cells = <1>;
#size-cells = <0>;
scmi_perf: protocol@13 {
reg = <0x13>;
#power-domain-cells = <1>;
};
};
};
clk_virt: interconnect-0 {
compatible = "qcom,glymur-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-1 {
compatible = "qcom,glymur-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd8: power-domain-cpu8 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd9: power-domain-cpu9 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd10: power-domain-cpu10 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd11: power-domain-cpu11 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd12: power-domain-cpu12 {
#power-domain-cells = <0>;
power-domains = <&cluster2_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd13: power-domain-cpu13 {
#power-domain-cells = <0>;
power-domains = <&cluster2_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd14: power-domain-cpu14 {
#power-domain-cells = <0>;
power-domains = <&cluster2_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd15: power-domain-cpu15 {
#power-domain-cells = <0>;
power-domains = <&cluster2_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd16: power-domain-cpu16 {
#power-domain-cells = <0>;
power-domains = <&cluster2_pd>;
domain-idle-states = <&cpu_c4>;
};
cpu_pd17: power-domain-cpu17 {
#power-domain-cells = <0>;
power-domains = <&cluster2_pd>;
domain-idle-states = <&cpu_c4>;
};
cluster0_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
power-domains = <&system_pd>;
domain-idle-states = <&cluster_cl5>;
};
cluster1_pd: power-domain-cpu-cluster1 {
#power-domain-cells = <0>;
power-domains = <&system_pd>;
domain-idle-states = <&cluster_cl5>;
};
cluster2_pd: power-domain-cpu-cluster2 {
#power-domain-cells = <0>;
power-domains = <&system_pd>;
domain-idle-states = <&cluster_cl5>;
};
system_pd: power-domain-system {
#power-domain-cells = <0>;
domain-idle-states = <&domain_ss3>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pdp_mem: pdp@81400000 {
reg = <0x0 0x81400000 0x0 0x100000>;
no-map;
};
aop_cmd_db_mem: aop-cmd-db@81c60000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x81c60000 0x0 0x20000>;
no-map;
};
pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
reg = <0x0 0x81e00000 0x0 0x200000>;
no-map;
};
oobdaretag_mem: oobdaretag@86e10000 {
reg = <0x0 0x86e10000 0x0 0x360000>;
no-map;
};
oob_secure_mem: oob-secure@87170000 {
reg = <0x0 0x87170000 0x0 0xbc0000>;
no-map;
};
oobdtbqc_mem: oobdtbqc@87d30000 {
reg = <0x0 0x87d30000 0x0 0x20000>;
no-map;
};
oobdtboem_mem: oobdtboem@87d50000 {
reg = <0x0 0x87d50000 0x0 0x20000>;
no-map;
};
oob_nonsecure_mem: oob-nonsecure@87e00000 {
reg = <0x0 0x87e00000 0x0 0xc00000>;
no-map;
};
spss_region_mem: spss@88a00000 {
reg = <0x0 0x88a00000 0x0 0x400000>;
no-map;
};
soccp_mem: soccp@88e00000 {
reg = <0x0 0x88e00000 0x0 0x400000>;
no-map;
};
soccpdtb_mem: soccpdtb@89200000 {
reg = <0x0 0x89200000 0x0 0x20000>;
no-map;
};
cvp_mem: cvp@89700000 {
reg = <0x0 0x89700000 0x0 0x700000>;
no-map;
};
adspslpi_mem: adspslpi@89e00000 {
reg = <0x0 0x89e00000 0x0 0x3a00000>;
no-map;
};
q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 {
reg = <0x0 0x8d800000 0x0 0x80000>;
no-map;
};
cdsp_mem: cdsp@8d900000 {
reg = <0x0 0x8d900000 0x0 0x4000000>;
no-map;
};
q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 {
reg = <0x0 0x91900000 0x0 0x80000>;
no-map;
};
gpu_microcode_mem: gpu-microcode@919fe000 {
reg = <0x0 0x919fe000 0x0 0x2000>;
no-map;
};
camera_mem: camera@91a00000 {
reg = <0x0 0x91a00000 0x0 0x800000>;
no-map;
};
av1_encoder_mem: av1-encoder@92200000 {
reg = <0x0 0x92200000 0x0 0x700000>;
no-map;
};
video_mem: video@92900000 {
reg = <0x0 0x92900000 0x0 0xc00000>;
no-map;
};
smem_mem: smem@ffe00000 {
compatible = "qcom,smem";
reg = <0x0 0xffe00000 0x0 0x200000>;
hwlocks = <&tcsr_mutex 3>;
no-map;
};
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x80000000 0x0 0x80000000>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_MPROC_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <443>, <429>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_MPROC_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <94>, <432>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-soccp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <617>, <616>;
qcom,local-pid = <0>;
qcom,remote-pid = <19>;
soccp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
soccp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
gcc: clock-controller@100000 {
compatible = "qcom,glymur-gcc";
reg = <0x0 0x00100000 0x0 0x1f9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */
<&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */
<&sleep_clk>, /* Sleep */
<0>, /* USB 0 Phy DP0 GMUX */
<0>, /* USB 0 Phy DP1 GMUX */
<0>, /* USB 0 Phy PCIE PIPEGMUX */
<0>, /* USB 0 Phy PIPEGMUX */
<0>, /* USB 0 Phy SYS PCIE PIPEGMUX */
<0>, /* USB 1 Phy DP0 GMUX 2 */
<0>, /* USB 1 Phy DP1 GMUX 2 */
<0>, /* USB 1 Phy PCIE PIPEGMUX */
<0>, /* USB 1 Phy PIPEGMUX */
<0>, /* USB 1 Phy SYS PCIE PIPEGMUX */
<0>, /* USB 2 Phy DP0 GMUX 2 */
<0>, /* USB 2 Phy DP1 GMUX 2 */
<0>, /* USB 2 Phy PCIE PIPEGMUX */
<0>, /* USB 2 Phy PIPEGMUX */
<0>, /* USB 2 Phy SYS PCIE PIPEGMUX */
<0>, /* PCIe 3a */
<0>, /* PCIe 3b */
<&pcie4_phy>, /* PCIe 4 */
<&pcie5_phy>, /* PCIe 5 */
<&pcie6_phy>, /* PCIe 6 */
<0>, /* QUSB4 0 PHY RX 0 */
<0>, /* QUSB4 0 PHY RX 1 */
<0>, /* QUSB4 1 PHY RX 0 */
<0>, /* QUSB4 1 PHY RX 1 */
<0>, /* QUSB4 2 PHY RX 0 */
<0>, /* QUSB4 2 PHY RX 1 */
<0>, /* UFS PHY RX Symbol 0 */
<0>, /* UFS PHY RX Symbol 1 */
<0>, /* UFS PHY TX Symbol 0 */
<&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */
<&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */
<0>, /* USB4 PHY 0 pcie pipe */
<0>, /* USB4 PHY 0 Max pipe */
<0>, /* USB4 PHY 1 pcie pipe */
<0>, /* USB4 PHY 1 Max pipe */
<0>, /* USB4 PHY 2 pcie */
<0>; /* USB4 PHY 2 Max */
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_CX>;
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00800000 0x0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
dma-channel-mask = <0x3f>;
#dma-cells = <3>;
iommus = <&apps_smmu 0xd76 0x0>;
};
qupv3_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x3000>;
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xd63 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
i2c16: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c16_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi16: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c17: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c17_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi17: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c18: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c18_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi18: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c19: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c19_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi19: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart19: serial@88c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart19_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c20: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c20_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi20: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c21: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c21_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi21: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart21: serial@894000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart21_default>;
pinctrl-names = "default";
};
i2c22: i2c@898000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
<&gpi_dma2 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c22_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi22: spi@898000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
<&gpi_dma2 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart22: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart22_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c23: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c23_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi23: spi@89c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00a00000 0x0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
dma-channel-mask = <0x3f>;
#dma-cells = <3>;
iommus = <&apps_smmu 0xcb6 0x0>;
};
qupv3_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x3000>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xca3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c8_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c9_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c10_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c11_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c12_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c13_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c14: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c14_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi14: spi@a98000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart14: serial@a98000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart14_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a9c000 0x0 0x4000>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c15_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi15: spi@a9c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a9c000 0x0 0x4000>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
<&gpi_dma1 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma0: dma-controller@b00000 {
compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00b00000 0x0 0x60000>;
interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
dma-channel-mask = <0x3f>;
#dma-cells = <3>;
iommus = <&apps_smmu 0xd36 0x0>;
};
qupv3_0: geniqup@bc0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00bc0000 0x0 0x3000>;
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xd23 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
i2c0: i2c@b80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b80000 0x0 0x4000>;
interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c0_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@b80000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b80000 0x0 0x4000>;
interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@b84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b84000 0x0 0x4000>;
interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c1_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@b84000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b84000 0x0 0x4000>;
interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@b88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b88000 0x0 0x4000>;
interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c2_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@b88000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b88000 0x0 0x4000>;
interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@b88000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00b88000 0x0 0x4000>;
interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart2_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c3: i2c@b8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b8c000 0x0 0x4000>;
interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c3_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@b8c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b8c000 0x0 0x4000>;
interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@b90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b90000 0x0 0x4000>;
interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c4_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@b90000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b90000 0x0 0x4000>;
interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@b94000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b94000 0x0 0x4000>;
interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c5_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@b94000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b94000 0x0 0x4000>;
interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@b98000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b98000 0x0 0x4000>;
interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c6_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@b98000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b98000 0x0 0x4000>;
interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@b9c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00b9c000 0x0 0x4000>;
interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c7_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi7: spi@b9c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00b9c000 0x0 0x4000>;
interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
remoteproc_soccp: remoteproc@d00000 {
compatible = "qcom,glymur-soccp-pas";
reg = <0x0 0x00d00000 0x0 0x200000>;
interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"pong";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MX>;
power-domain-names = "cx",
"mx";
memory-region = <&soccp_mem>,
<&soccpdtb_mem>;
qcom,smem-states = <&soccp_smp2p_out 0>,
<&soccp_smp2p_out 8>;
qcom,smem-state-names = "stop",
"ping";
glink-edge {
interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <19>;
label = "soccp";
};
};
usb_hs_phy: phy@fa0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x00fa0000 0x0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
status = "disabled";
};
usb_mp_hsphy0: phy@fa1000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x00fa1000 0x0 0x29c>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
status = "disabled";
};
usb_mp_hsphy1: phy@fa2000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x00fa2000 0x0 0x29c>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
status = "disabled";
};
usb_mp_qmpphy0: phy@fa3000 {
compatible = "qcom,glymur-qmp-usb3-uni-phy";
reg = <0x0 0x00fa3000 0x0 0x2000>;
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
<&tcsr TCSR_USB3_0_CLKREF_EN>,
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"pipe";
power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>,
<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
reset-names = "phy",
"phy_phy";
clock-output-names = "usb3_uni_phy_0_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
usb_mp_qmpphy1: phy@fa5000 {
compatible = "qcom,glymur-qmp-usb3-uni-phy";
reg = <0x0 0x00fa5000 0x0 0x2000>;
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
<&tcsr TCSR_USB3_1_CLKREF_EN>,
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"pipe";
power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>,
<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
reset-names = "phy",
"phy_phy";
clock-output-names = "usb3_uni_phy_1_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
mdss_dp3_phy: phy@faac00 {
compatible = "qcom,glymur-dp-phy";
reg = <0x0 0x00faac00 0x0 0x1d0>,
<0x0 0x00faa400 0x0 0x128>,
<0x0 0x00faa800 0x0 0x128>,
<0x0 0x00faa000 0x0 0x358>;
clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb",
"ref";
power-domains = <&rpmhpd RPMHPD_MX>;
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
usb_0_hsphy: phy@fd3000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x00fd3000 0x0 0x29c>;
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
status = "disabled";
};
usb_0_qmpphy: phy@fd5000 {
compatible = "qcom,glymur-qmp-usb3-dp-phy";
reg = <0x0 0x00fd5000 0x0 0x8000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
reset-names = "phy",
"common";
power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
#clock-cells = <1>;
#phy-cells = <1>;
mode-switch;
orientation-switch;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_0_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_0_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_0_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
remote-endpoint = <&mdss_dp0_out>;
};
};
};
};
usb_1_hsphy: phy@fdd000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x00fdd000 0x0 0x29c>;
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
status = "disabled";
};
usb_1_qmpphy: phy@fde000 {
compatible = "qcom,glymur-qmp-usb3-dp-phy";
reg = <0x0 0x00fde000 0x0 0x8000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&tcsr TCSR_USB4_1_CLKREF_EN>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
reset-names = "phy",
"common";
#clock-cells = <1>;
#phy-cells = <1>;
mode-switch;
orientation-switch;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_1_qmpphy_dp_in: endpoint {
remote-endpoint = <&mdss_dp1_out>;
};
};
};
};
/* cluster0 */
bwmon_cluster0: pmu@100c400 {
compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x0100c400 0x0 0x600>;
interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
cpu_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
opp-0 {
opp-peak-kBps = <800000>;
};
opp-1 {
opp-peak-kBps = <2188800>;
};
opp-2 {
opp-peak-kBps = <5414400>;
};
opp-3 {
opp-peak-kBps = <6220800>;
};
opp-4 {
opp-peak-kBps = <6835200>;
};
opp-5 {
opp-peak-kBps = <8371200>;
};
opp-6 {
opp-peak-kBps = <10944000>;
};
opp-7 {
opp-peak-kBps = <12748800>;
};
opp-8 {
opp-peak-kBps = <14745600>;
};
opp-9 {
opp-peak-kBps = <16896000>;
};
opp-10 {
opp-peak-kBps = <19046400>;
};
opp-11 {
opp-peak-kBps = <21332000>;
};
};
};
/* cluster1 */
bwmon_cluster1: pmu@100d400 {
compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x0100d400 0x0 0x600>;
interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
};
/* cluster2 */
bwmon_cluster2: pmu@100e400 {
compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x0100e400 0x0 0x600>;
interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
};
cnoc_main: interconnect@1500000 {
compatible = "qcom,glymur-cnoc-main";
reg = <0x0 0x01500000 0x0 0x17080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
config_noc: interconnect@1600000 {
compatible = "qcom,glymur-cnoc-cfg";
reg = <0x0 0x01600000 0x0 0x6600>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,glymur-system-noc";
reg = <0x0 0x01680000 0x0 0x1c080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
pcie_west_anoc: interconnect@16c0000 {
compatible = "qcom,glymur-pcie-west-anoc";
reg = <0x0 0x016c0000 0x0 0xf580>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
};
pcie_east_anoc: interconnect@16d0000 {
compatible = "qcom,glymur-pcie-east-anoc";
reg = <0x0 0x016d0000 0x0 0xf300>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,glymur-aggre1-noc";
reg = <0x0 0x016e0000 0x0 0x14400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
aggre2_noc: interconnect@1720000 {
compatible = "qcom,glymur-aggre2-noc";
reg = <0x0 0x01720000 0x0 0x14400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_2_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
};
aggre3_noc: interconnect@1700000 {
compatible = "qcom,glymur-aggre3-noc";
reg = <0x0 0x01700000 0x0 0x1d400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
aggre4_noc: interconnect@1740000 {
compatible = "qcom,glymur-aggre4-noc";
reg = <0x0 0x01740000 0x0 0x14400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
};
mmss_noc: interconnect@1780000 {
compatible = "qcom,glymur-mmss-noc";
reg = <0x0 0x01780000 0x0 0x5b800>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
pcie_east_slv_noc: interconnect@1900000 {
compatible = "qcom,glymur-pcie-east-slv-noc";
reg = <0x0 0x01900000 0x0 0xe080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
pcie_west_slv_noc: interconnect@1920000 {
compatible = "qcom,glymur-pcie-west-slv-noc";
reg = <0x0 0x01920000 0x0 0xf180>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
pcie4: pcie@1bf0000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01bf0000 0x0 0x3000>,
<0x0 0x78000000 0x0 0xf20>,
<0x0 0x78000f40 0x0 0xa8>,
<0x0 0x78001000 0x0 0x4000>,
<0x0 0x78005000 0x0 0x100000>,
<0x0 0x01bf3000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>,
<0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>,
<0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <4>;
num-lanes = <2>;
operating-points-v2 = <&pcie4_opp_table>;
msi-map = <0x0 &gic_its 0xc0000 0x10000>;
iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>;
interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
<&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_4_SLV_AXI_CLK>,
<&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"noc_aggr";
assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem",
"cpu-pcie";
resets = <&gcc GCC_PCIE_4_BCR>,
<&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc GCC_PCIE_4_GDSC>;
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
status = "disabled";
pcie4_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000-1 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
opp-level = <1>;
};
/* GEN 1 x2 */
opp-5000000-1 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <1>;
};
/* GEN 2 x1 */
opp-5000000-2 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <2>;
};
/* GEN 2 x2 */
opp-10000000-2 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
opp-level = <2>;
};
/* GEN 3 x1 */
opp-8000000-3 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <984500 1>;
opp-level = <3>;
};
/* GEN 3 x2 */
opp-16000000-3 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <3>;
};
/* GEN 4 x1 */
opp-16000000-4 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <4>;
};
/* GEN 4 x2 */
opp-32000000-4 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <3938000 1>;
opp-level = <4>;
};
};
pcie4_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie4_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie4_port0_ep: endpoint {
};
};
};
};
pcie4_phy: phy@1bf6000 {
compatible = "qcom,glymur-qmp-gen4x2-pcie-phy";
reg = <0x0 0x01bf6000 0x0 0x2000>;
clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>,
<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_2_CLKREF_EN>,
<&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_4_PIPE_CLK>,
<&gcc GCC_PCIE_4_PIPE_DIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_4_PHY_BCR>,
<&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie4_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
pcie5: pcie@1b40000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01b40000 0x0 0x3000>,
<0x0 0x7a000000 0x0 0xf20>,
<0x0 0x7a000f40 0x0 0xa8>,
<0x0 0x7a001000 0x0 0x4000>,
<0x0 0x7a100000 0x0 0x100000>,
<0x0 0x01b43000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>,
<0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>,
<0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <5>;
num-lanes = <4>;
operating-points-v2 = <&pcie5_opp_table>;
msi-map = <0x0 &gic_its 0xd0000 0x10000>;
iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>;
interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
<&gcc GCC_PCIE_5_CFG_AHB_CLK>,
<&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_5_SLV_AXI_CLK>,
<&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"noc_aggr";
assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem",
"cpu-pcie";
resets = <&gcc GCC_PCIE_5_BCR>,
<&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc GCC_PCIE_5_GDSC>;
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
status = "disabled";
pcie5_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000-1 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
opp-level = <1>;
};
/* GEN 1 x2 */
opp-5000000-1 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <1>;
};
/* GEN 1 x4 */
opp-10000000-1 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
opp-level = <1>;
};
/* GEN 2 x1 */
opp-5000000-2 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <2>;
};
/* GEN 2 x2 */
opp-10000000-2 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
opp-level = <2>;
};
/* GEN 2 x4 */
opp-20000000-2 {
opp-hz = /bits/ 64 <20000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <2000000 1>;
opp-level = <2>;
};
/* GEN 3 x1 */
opp-8000000-3 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <984500 1>;
opp-level = <3>;
};
/* GEN 3 x2 */
opp-16000000-3 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <3>;
};
/* GEN 3 x4 */
opp-32000000-3 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <3938000 1>;
opp-level = <3>;
};
/* GEN 4 x1 */
opp-16000000-4 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <4>;
};
/* GEN 4 x2 */
opp-32000000-4 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <3938000 1>;
opp-level = <4>;
};
/* GEN 4 x4 */
opp-64000000-4 {
opp-hz = /bits/ 64 <64000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <7876000 1>;
opp-level = <4>;
};
/* GEN 5 x1 */
opp-32000000-5 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <3938000 1>;
opp-level = <5>;
};
/* GEN 5 x2 */
opp-64000000-5 {
opp-hz = /bits/ 64 <64000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <7876000 1>;
opp-level = <5>;
};
/* GEN 5 x4 */
opp-128000000-5 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <15753000 1>;
opp-level = <5>;
};
};
pcie5_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie5_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie5_port0_ep: endpoint {
};
};
};
};
pcie5_phy: phy@1b50000 {
compatible = "qcom,glymur-qmp-gen5x4-pcie-phy";
reg = <0x0 0x01b50000 0x0 0x10000>;
clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>,
<&gcc GCC_PCIE_5_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_1_CLKREF_EN>,
<&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_5_PIPE_CLK>,
<&gcc GCC_PCIE_5_PIPE_DIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_5_PHY_BCR>,
<&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie5_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
pcie6: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x7e000000 0x0 0xf20>,
<0x0 0x7e000f40 0x0 0xa8>,
<0x0 0x7e001000 0x0 0x4000>,
<0x0 0x7e100000 0x0 0x100000>,
<0x0 0x01c03000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
<0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>,
<0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <6>;
num-lanes = <2>;
operating-points-v2 = <&pcie6_opp_table>;
msi-map = <0x0 &gic_its 0xe0000 0x10000>;
iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>;
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_6_AUX_CLK>,
<&gcc GCC_PCIE_6_CFG_AHB_CLK>,
<&gcc GCC_PCIE_6_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_6_SLV_AXI_CLK>,
<&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"noc_aggr";
assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem",
"cpu-pcie";
resets = <&gcc GCC_PCIE_6_BCR>,
<&gcc GCC_PCIE_6_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc GCC_PCIE_6_GDSC>;
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
status = "disabled";
pcie6_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000-1 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
opp-level = <1>;
};
/* GEN 1 x2 */
opp-5000000-1 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <1>;
};
/* GEN 2 x1 */
opp-5000000-2 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <2>;
};
/* GEN 2 x2 */
opp-10000000-2 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
opp-level = <2>;
};
/* GEN 3 x1 */
opp-8000000-3 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <984500 1>;
opp-level = <3>;
};
/* GEN 3 x2 */
opp-16000000-3 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <3>;
};
/* GEN 4 x1 */
opp-16000000-4 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <4>;
};
/* GEN 4 x2 */
opp-32000000-4 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <3938000 1>;
opp-level = <4>;
};
};
pcie6_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie6_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie6_port0_ep: endpoint {
};
};
};
};
pcie6_phy: phy@1c06000 {
compatible = "qcom,glymur-qmp-gen4x2-pcie-phy";
reg = <0x0 0x01c06000 0x0 0x2000>;
clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>,
<&gcc GCC_PCIE_6_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_4_CLKREF_EN>,
<&gcc GCC_PCIE_6_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_6_PIPE_CLK>,
<&gcc GCC_PCIE_6_PIPE_DIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_6_PHY_BCR>,
<&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie6_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
pcie3b: pcie@1b80000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01b80000 0x0 0x3000>,
<0x0 0x74000000 0x0 0xf20>,
<0x0 0x74000f40 0x0 0xa8>,
<0x0 0x74001000 0x0 0x4000>,
<0x0 0x74100000 0x0 0x100000>,
<0x0 0x01b83000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>,
<0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>,
<0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <7>;
num-lanes = <4>;
operating-points-v2 = <&pcie3b_opp_table>;
msi-map = <0x0 &gic_its 0xf0000 0x10000>;
iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>;
interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
<&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
<&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"noc_aggr";
assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem",
"cpu-pcie";
resets = <&gcc GCC_PCIE_3B_BCR>,
<&gcc GCC_PCIE_3B_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc GCC_PCIE_3B_GDSC>;
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
status = "disabled";
pcie3b_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000-1 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
opp-level = <1>;
};
/* GEN 1 x2 */
opp-5000000-1 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <1>;
};
/* GEN 1 x4 */
opp-10000000-1 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
opp-level = <1>;
};
/* GEN 2 x1 */
opp-5000000-2 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
opp-level = <2>;
};
/* GEN 2 x2 */
opp-10000000-2 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
opp-level = <2>;
};
/* GEN 2 x4 */
opp-20000000-2 {
opp-hz = /bits/ 64 <20000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <2000000 1>;
opp-level = <2>;
};
/* GEN 3 x1 */
opp-8000000-3 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <984500 1>;
opp-level = <3>;
};
/* GEN 3 x2 */
opp-16000000-3 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <3>;
};
/* GEN 3 x4 */
opp-32000000-3 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <3938000 1>;
opp-level = <3>;
};
/* GEN 4 x1 */
opp-16000000-4 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <1969000 1>;
opp-level = <4>;
};
/* GEN 4 x2 */
opp-32000000-4 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <3938000 1>;
opp-level = <4>;
};
/* GEN 4 x4 */
opp-64000000-4 {
opp-hz = /bits/ 64 <64000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <7876000 1>;
opp-level = <4>;
};
/* GEN 5 x1 */
opp-32000000-5 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <3938000 1>;
opp-level = <5>;
};
/* GEN 5 x2 */
opp-64000000-5 {
opp-hz = /bits/ 64 <64000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <7876000 1>;
opp-level = <5>;
};
/* GEN 5 x4 */
opp-128000000-5 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <15753000 1>;
opp-level = <5>;
};
};
pcie3b_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie3b_port0_ep: endpoint {
};
};
};
};
rng: rng@10c3000 {
compatible = "qcom,glymur-trng", "qcom,trng";
reg = <0x0 0x010c3000 0x0 0x1000>;
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&apps_smmu 0x80 0x0>,
<&apps_smmu 0x81 0x0>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <20>;
qcom,num-ees = <4>;
};
crypto: crypto@1dfa000 {
compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx",
"tx";
iommus = <&apps_smmu 0x80 0x0>,
<&apps_smmu 0x81 0x0>;
interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "memory";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
#hwlock-cells = <1>;
};
tcsr: clock-controller@1fd5000 {
compatible = "qcom,glymur-tcsr",
"syscon";
reg = <0x0 0x1fd5000 0x0 0x21000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};
hsc_noc: interconnect@2000000 {
compatible = "qcom,glymur-hscnoc";
reg = <0x0 0x02000000 0x0 0x93a080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
gpu: gpu@3d00000 {
compatible = "qcom,adreno-44070001", "qcom,adreno";
reg = <0x0 0x03d00000 0x0 0x6c000>,
<0x0 0x03d9e000 0x0 0x2000>;
reg-names = "kgsl_3d0_reg_memory",
"cx_mem";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0x0>,
<&adreno_smmu 1 0x0>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "gfx-mem";
gpu_opp_table: opp-table {
compatible = "operating-points-v2-adreno",
"operating-points-v2";
opp-310000000 {
opp-hz = /bits/ 64 <310000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <2136719>;
opp-supported-hw = <0xf>;
/* ACD is disabled */
};
opp-410000000 {
opp-hz = /bits/ 64 <410000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <6074219>;
opp-supported-hw = <0xf>;
/* ACD is disabled */
};
opp-572000000 {
opp-hz = /bits/ 64 <572000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <12449219>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0xe02d5ffd>;
};
opp-760000000 {
opp-hz = /bits/ 64 <760000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <12449219>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0xc0285ffd>;
};
opp-820000000 {
opp-hz = /bits/ 64 <820000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <16500000>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0xa82e5ffd>;
};
opp-915000000 {
opp-hz = /bits/ 64 <915000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <16500000>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0x882d5ffd>;
};
opp-1070000000 {
opp-hz = /bits/ 64 <1070000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <16500000>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0x882b5ffd>;
};
opp-1185000000 {
opp-hz = /bits/ 64 <1185000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <16500000>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0x882a5ffd>;
};
opp-1350000000 {
opp-hz = /bits/ 64 <1350000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <18597657>;
opp-supported-hw = <0xf>;
qcom,opp-acd-level = <0x882a5ffd>;
};
opp-1550000000 {
opp-hz = /bits/ 64 <1550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
opp-peak-kBps = <18597657>;
opp-supported-hw = <0x7>;
qcom,opp-acd-level = <0xa8295ffd>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
opp-peak-kBps = <18597657>;
opp-supported-hw = <0x7>;
qcom,opp-acd-level = <0x88295ffd>;
};
opp-1850000000 {
opp-hz = /bits/ 64 <1850000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
opp-peak-kBps = <18597657>;
opp-supported-hw = <0x3>;
qcom,opp-acd-level = <0x88285ffd>;
};
};
};
gxclkctl: clock-controller@3d64000 {
compatible = "qcom,glymur-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
power-domains = <&rpmhpd RPMHPD_GFX>,
<&rpmhpd RPMHPD_GMXC>,
<&gpucc GPU_CC_CX_GDSC>;
#power-domain-cells = <1>;
};
gmu: gmu@3d6c000 {
compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
reg = <0x0 0x03d6c000 0x0 0x32000>;
reg-names = "gmu";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi",
"gmu";
clocks = <&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
<&gpucc GPU_CC_RSCC_HUB_AON_CLK>;
clock-names = "ahb",
"gmu",
"cxo",
"memnoc",
"hub",
"rscc";
power-domains = <&gpucc GPU_CC_CX_GDSC>,
<&gxclkctl GX_CLKCTL_GX_GDSC>;
power-domain-names = "cx",
"gx";
iommus = <&adreno_smmu 5 0x0>;
qcom,qmp = <&aoss_qmp>;
operating-points-v2 = <&gmu_opp_table>;
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-575000000 {
opp-hz = /bits/ 64 <575000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
opp-725000000 {
opp-hz = /bits/ 64 <725000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
};
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,glymur-gpucc";
reg = <0x0 0x03d90000 0x0 0x9800>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
power-domains = <&rpmhpd RPMHPD_MX>,
<&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
adreno_smmu: iommu@3da0000 {
compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
clock-names = "hlos";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
dma-coherent;
};
ipcc: mailbox@3e04000 {
compatible = "qcom,glymur-ipcc", "qcom,ipcc";
reg = <0x0 0x03e04000 0x0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
remoteproc_adsp: remoteproc@6800000 {
compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas";
reg = <0x0 0x06800000 0x0 0x10000>;
iommus = <&apps_smmu 0x1000 0x0>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx",
"lmx";
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_MPROC_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <2>;
label = "lpass";
fastrpc {
compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
memory-region = <&adsp_rpc_remote_heap_mem>;
qcom,vmids = <QCOM_SCM_VMID_LPASS
QCOM_SCM_VMID_ADSP_HEAP>;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1063 0x20>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1064 0x20>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1065 0x20>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1066 0x20>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x40>,
<&apps_smmu 0x1067 0x0>,
<&apps_smmu 0x1087 0x0>;
dma-coherent;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x1008 0x80>,
<&apps_smmu 0x1068 0x20>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1061 0x20>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
swr0: soundwire@6c80000 {
compatible = "qcom,soundwire-v3.1.0";
reg = <0x0 0x06c80000 0x0 0x10000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsamacro>;
clock-names = "iface";
label = "WSA";
pinctrl-0 = <&wsa_swr_active>;
pinctrl-names = "default";
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_wsamacro: codec@6c90000 {
compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06c90000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
sound-name-prefix = "WSA";
};
swr3: soundwire@6ca0000 {
compatible = "qcom,soundwire-v3.1.0";
reg = <0x0 0x06ca0000 0x0 0x10000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsa2macro>;
clock-names = "iface";
label = "WSA2";
pinctrl-0 = <&wsa2_swr_active>;
pinctrl-names = "default";
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_wsa2macro: codec@6cb0000 {
compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06cb0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
#sound-dai-cells = <1>;
sound-name-prefix = "WSA2";
};
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,glymur-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
lpass_lpicx_noc: interconnect@7420000 {
compatible = "qcom,glymur-lpass-lpicx-noc";
reg = <0x0 0x07420000 0x0 0x44080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
lpass_vamacro: codec@7660000 {
compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
reg = <0x0 0x07660000 0x0 0x2000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk",
"macro",
"dcodec";
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
};
lpass_tlmm: pinctrl@7760000 {
compatible = "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-pinctrl";
reg = <0x0 0x07760000 0x0 0x20000>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
tx_swr_active: tx-swr-active-state {
clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio1", "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
rx_swr_active: rx-swr-active-state {
clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
dmic01_default: dmic01-default-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
wsa2_swr_active: wsa2-swr-active-state {
clk-pins {
pins = "gpio15";
function = "wsa2_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio16";
function = "wsa2_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
};
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,glymur-lpass-ag-noc";
reg = <0x0 0x07e40000 0x0 0xe080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
usb_2_hsphy: phy@88e0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x088e0000 0x0 0x29c>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
status = "disabled";
};
usb_2_qmpphy: phy@88e1000 {
compatible = "qcom,glymur-qmp-usb3-dp-phy";
reg = <0x0 0x088e1000 0x0 0x8000>;
clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
<&tcsr TCSR_USB4_2_CLKREF_EN>,
<&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
<&gcc GCC_USB3PHY_PHY_TERT_BCR>;
reset-names = "phy",
"common";
#clock-cells = <1>;
#phy-cells = <1>;
mode-switch;
orientation-switch;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_2_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_2_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_2_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_2_qmpphy_dp_in: endpoint {
remote-endpoint = <&mdss_dp2_out>;
};
};
};
};
usb_0: usb@a600000 {
compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a600000 0x0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr_north",
"noc_aggr_south";
interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 90 IRQ_TYPE_EDGE_BOTH>,
<&pdc 60 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
iommus = <&apps_smmu 0x1420 0x0>;
phys = <&usb_0_hsphy>,
<&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,has-lpm-erratum;
tx-fifo-resize;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_0_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_0_dwc3_ss: endpoint {
remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
};
};
};
};
usb_1: usb@a800000 {
compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a800000 0x0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr_north",
"noc_aggr_south";
interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 88 IRQ_TYPE_EDGE_BOTH>,
<&pdc 87 IRQ_TYPE_EDGE_BOTH>,
<&pdc 76 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
iommus = <&apps_smmu 0x1460 0x0>;
phys = <&usb_1_hsphy>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,has-lpm-erratum;
tx-fifo-resize;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
};
};
};
usb_2: usb@a000000 {
compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a000000 0x0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
<&gcc GCC_USB30_TERT_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
<&gcc GCC_USB30_TERT_SLEEP_CLK>,
<&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr_north",
"noc_aggr_south";
interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 89 IRQ_TYPE_EDGE_BOTH>,
<&pdc 81 IRQ_TYPE_EDGE_BOTH>,
<&pdc 75 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
resets = <&gcc GCC_USB30_TERT_BCR>;
power-domains = <&gcc GCC_USB30_TERT_GDSC>;
iommus = <&apps_smmu 0x420 0x0>;
phys = <&usb_2_hsphy>,
<&usb_2_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,has-lpm-erratum;
tx-fifo-resize;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_2_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_2_dwc3_ss: endpoint {
remote-endpoint = <&usb_2_qmpphy_usb_ss_in>;
};
};
};
};
usb_hs: usb@a200000 {
compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a200000 0x0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
<&gcc GCC_USB20_SLEEP_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr_north",
"noc_aggr_south";
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 92 IRQ_TYPE_EDGE_BOTH>,
<&pdc 57 IRQ_TYPE_EDGE_BOTH>,
<&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"hs_phy_irq";
resets = <&gcc GCC_USB20_PRIM_BCR>;
power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
iommus = <&apps_smmu 0x0ce0 0x0>;
interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr",
"apps-usb";
phys = <&usb_hs_phy>;
phy-names = "usb2-phy";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,has-lpm-erratum;
tx-fifo-resize;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
maximum-speed = "high-speed";
qcom,select-utmi-as-pipe-clk;
usb-role-switch;
wakeup-source;
status = "disabled";
};
usb_mp: usb@a400000 {
compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3";
reg = <0x0 0x0a400000 0x0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
<&gcc GCC_USB30_MP_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
<&gcc GCC_USB30_MP_SLEEP_CLK>,
<&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr_north",
"noc_aggr_south";
interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 11 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 78 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwc_usb3",
"pwr_event_1",
"pwr_event_2",
"hs_phy_1",
"hs_phy_2",
"dp_hs_phy_1",
"dm_hs_phy_1",
"dp_hs_phy_2",
"dm_hs_phy_2",
"ss_phy_1",
"ss_phy_2";
resets = <&gcc GCC_USB30_MP_BCR>;
power-domains = <&gcc GCC_USB30_MP_GDSC>;
iommus = <&apps_smmu 0xda0 0x0>;
phys = <&usb_mp_hsphy0>,
<&usb_mp_qmpphy0>,
<&usb_mp_hsphy1>,
<&usb_mp_qmpphy1>;
phy-names = "usb2-0",
"usb3-0",
"usb2-1",
"usb3-1";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,has-lpm-erratum;
tx-fifo-resize;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
dr_mode = "host";
wakeup-source;
status = "disabled";
};
camcc: clock-controller@ade0000 {
compatible = "qcom,glymur-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss: display-subsystem@ae00000 {
compatible = "qcom,glymur-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
reg-names = "mdss";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
iommus = <&apps_smmu 0x1de0 0x2>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,glymur-dpu";
reg = <0x0 0x0ae01000 0x0 0x93000>,
<0x0 0x0aeb0000 0x0 0x3000>;
reg-names = "mdp",
"vbif";
interrupts-extended = <&mdss 0>;
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "nrt_bus",
"iface",
"lut",
"core",
"vsync";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss_dp0_in>;
};
};
port@4 {
reg = <4>;
mdss_intf4_out: endpoint {
remote-endpoint = <&mdss_dp1_in>;
};
};
port@5 {
reg = <5>;
mdss_intf5_out: endpoint {
remote-endpoint = <&mdss_dp3_in>;
};
};
port@6 {
reg = <6>;
mdss_intf6_out: endpoint {
remote-endpoint = <&mdss_dp2_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-156000000 {
opp-hz = /bits/ 64 <156000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>;
};
opp-205000000 {
opp-hz = /bits/ 64 <205000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-337000000 {
opp-hz = /bits/ 64 <337000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-417000000 {
opp-hz = /bits/ 64 <417000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-532000000 {
opp-hz = /bits/ 64 <532000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
required-opps = <&rpmhpd_opp_nom_l1>;
};
opp-660000000 {
opp-hz = /bits/ 64 <660000000>;
required-opps = <&rpmhpd_opp_turbo>;
};
opp-717000000 {
opp-hz = /bits/ 64 <717000000>;
required-opps = <&rpmhpd_opp_turbo_l1>;
};
};
};
mdss_dp0: displayport-controller@af54000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0xaf54000 0x0 0x200>,
<0x0 0xaf54200 0x0 0x200>,
<0x0 0xaf55000 0x0 0xc00>,
<0x0 0xaf56000 0x0 0x400>,
<0x0 0xaf57000 0x0 0x400>,
<0x0 0xaf58000 0x0 0x400>,
<0x0 0xaf59000 0x0 0x400>,
<0x0 0xaf5a000 0x0 0x600>,
<0x0 0xaf5b000 0x0 0x600>;
interrupts-extended = <&mdss 12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dp0_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
mdss_dp0_out: endpoint {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
};
};
mdss_dp0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-675000000 {
opp-hz = /bits/ 64 <675000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_dp1: displayport-controller@af5c000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0xaf5c000 0x0 0x200>,
<0x0 0xaf5c200 0x0 0x200>,
<0x0 0xaf5d000 0x0 0xc00>,
<0x0 0xaf5e000 0x0 0x400>,
<0x0 0xaf5f000 0x0 0x400>,
<0x0 0xaf60000 0x0 0x400>,
<0x0 0xaf61000 0x0 0x400>,
<0x0 0xaf62000 0x0 0x600>,
<0x0 0xaf63000 0x0 0x600>;
interrupts-extended = <&mdss 13>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dp1_in: endpoint {
remote-endpoint = <&mdss_intf4_out>;
};
};
port@1 {
reg = <1>;
mdss_dp1_out: endpoint {
remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
};
};
};
mdss_dp2: displayport-controller@af64000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0x0af64000 0x0 0x200>,
<0x0 0x0af64200 0x0 0x200>,
<0x0 0x0af65000 0x0 0xc00>,
<0x0 0x0af66000 0x0 0x400>,
<0x0 0x0af67000 0x0 0x400>,
<0x0 0x0af68000 0x0 0x400>,
<0x0 0x0af69000 0x0 0x400>,
<0x0 0x0af6a000 0x0 0x600>,
<0x0 0x0af6b000 0x0 0x600>;
interrupts-extended = <&mdss 14>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dp2_in: endpoint {
remote-endpoint = <&mdss_intf6_out>;
};
};
port@1 {
reg = <1>;
mdss_dp2_out: endpoint {
remote-endpoint = <&usb_2_qmpphy_dp_in>;
};
};
};
};
mdss_dp3: displayport-controller@af6c000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0x0af6c000 0x0 0x200>,
<0x0 0x0af6c200 0x0 0x200>,
<0x0 0x0af6d000 0x0 0xc00>,
<0x0 0x0af6e000 0x0 0x400>,
<0x0 0x0af6f000 0x0 0x400>,
<0x0 0x0af70000 0x0 0x400>,
<0x0 0x0af71000 0x0 0x400>,
<0x0 0x0af72000 0x0 0x600>,
<0x0 0x0af73000 0x0 0x600>;
interrupts-extended = <&mdss 15>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss_dp3_phy 0>,
<&mdss_dp3_phy 1>;
operating-points-v2 = <&mdss_dp0_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dp3_phy>;
phy-names = "dp";
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dp3_in: endpoint {
remote-endpoint = <&mdss_intf5_out>;
};
};
port@1 {
reg = <1>;
mdss_dp3_out: endpoint {
};
};
};
};
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,glymur-videocc";
reg = <0x0 0x0aaf0000 0x0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
evacc: clock-controller@abf0000 {
compatible = "qcom,glymur-evacc";
reg = <0x0 0x0abf0000 0x0 0x10000>;
clocks = <&gcc GCC_EVA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,glymur-dispcc";
reg = <0x0 0x0af00000 0x0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
<&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&mdss_dp3_phy 0>, /* dp3 */
<&mdss_dp3_phy 1>,
<0>, /* dsi0 */
<0>,
<0>, /* dsi1 */
<0>,
<0>,
<0>,
<0>,
<0>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,glymur-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>;
qcom,pdc-ranges = <0 745 38>,
<40 785 11>,
<51 527 4>,
<57 533 10>,
<70 546 4>,
<75 551 18>,
<108 619 22>,
<130 717 12>,
<142 251 5>,
<147 796 16>,
<171 4104 36>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
tsens0: thermal-sensor@c22c000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c22c000 0x0 0x1000>,
<0x0 0x0c222000 0x0 0x1000>;
interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c22d000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c22d000 0x0 0x1000>,
<0x0 0x0c223000 0x0 0x1000>;
interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <9>;
#thermal-sensor-cells = <1>;
};
tsens2: thermal-sensor@c22e000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c22e000 0x0 0x1000>,
<0x0 0x0c224000 0x0 0x1000>;
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens3: thermal-sensor@c22f000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c22f000 0x0 0x1000>,
<0x0 0x0c225000 0x0 0x1000>;
interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
tsens4: thermal-sensor@c230000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c230000 0x0 0x1000>,
<0x0 0x0c226000 0x0 0x1000>;
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens5: thermal-sensor@c231000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c231000 0x0 0x1000>,
<0x0 0x0c227000 0x0 0x1000>;
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
tsens6: thermal-sensor@c232000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c232000 0x0 0x1000>,
<0x0 0x0c228000 0x0 0x1000>;
interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens7: thermal-sensor@c233000 {
compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c233000 0x0 0x1000>,
<0x0 0x0c229000 0x0 0x1000>;
interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow",
"critical";
#qcom,sensors = <15>;
#thermal-sensor-cells = <1>;
};
aoss_qmp: power-management@c300000 {
compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
interrupt-parent = <&ipcc>;
interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
};
sram@c30f000 {
compatible = "qcom,rpmh-stats";
reg = <0x0 0x0c30f000 0x0 0x400>;
};
arbiter@c400000 {
compatible = "qcom,glymur-spmi-pmic-arb";
reg = <0x0 0x0c400000 0x0 0x3000>,
<0x0 0x0c900000 0x0 0x400000>,
<0x0 0x0c4c0000 0x0 0x400000>,
<0x0 0x0c403000 0x0 0x8000>;
reg-names = "core",
"chnls",
"obsrvr",
"chnl_map";
#address-cells = <2>;
#size-cells = <2>;
ranges;
qcom,channel = <0>;
qcom,ee = <0>;
spmi_bus0: spmi@c426000 {
reg = <0x0 0x0c426000 0x0 0x4000>,
<0x0 0x0c8c0000 0x0 0x10000>,
<0x0 0x0c42a000 0x0 0x8000>;
reg-names = "cnfg",
"intr",
"chnl_owner";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
};
spmi_bus1: spmi@c437000 {
reg = <0x0 0x0c437000 0x0 0x4000>,
<0x0 0x0c8d0000 0x0 0x10000>,
<0x0 0x0c43b000 0x0 0x8000>;
reg-names = "cnfg",
"intr",
"chnl_owner";
interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
};
spmi_bus2: spmi@c448000 {
reg = <0x0 0x0c448000 0x0 0x4000>,
<0x0 0x0c8e0000 0x0 0x10000>,
<0x0 0x0c44c000 0x0 0x8000>;
reg-names = "cnfg",
"intr",
"chnl_owner";
interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
};
};
tlmm: pinctrl@f100000 {
compatible = "qcom,glymur-tlmm";
reg = <0x0 0x0f100000 0x0 0xf00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 249>;
wakeup-parent = <&pdc>;
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio0", "gpio1";
function = "qup0_se0";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
/* SDA, SCL */
pins = "gpio4", "gpio5";
function = "qup0_se1";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
/* SDA, SCL */
pins = "gpio8", "gpio9";
function = "qup0_se2";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
/* SDA, SCL */
pins = "gpio12", "gpio13";
function = "qup0_se3";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
/* SDA, SCL */
pins = "gpio16", "gpio17";
function = "qup0_se4";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
/* SDA, SCL */
pins = "gpio20", "gpio21";
function = "qup0_se5";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
/* SDA, SCL */
pins = "gpio6", "gpio7";
function = "qup0_se6";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
/* SDA, SCL */
pins = "gpio14", "gpio15";
function = "qup0_se7";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
/* SDA, SCL */
pins = "gpio32", "gpio33";
function = "qup1_se0";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c9_data_clk: qup-i2c9-data-clk-state {
/* SDA, SCL */
pins = "gpio36", "gpio37";
function = "qup1_se1";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
/* SDA, SCL */
pins = "gpio40", "gpio41";
function = "qup1_se2";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
/* SDA, SCL */
pins = "gpio44", "gpio45";
function = "qup1_se3";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
/* SDA, SCL */
pins = "gpio48", "gpio49";
function = "qup1_se4";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
/* SDA, SCL */
pins = "gpio52", "gpio53";
function = "qup1_se5";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c14_data_clk: qup-i2c14-data-clk-state {
/* SDA, SCL */
pins = "gpio56", "gpio57";
function = "qup1_se6";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
/* SDA, SCL */
pins = "gpio54", "gpio55";
function = "qup1_se7";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c16_data_clk: qup-i2c16-data-clk-state {
/* SDA, SCL */
pins = "gpio64", "gpio65";
function = "qup2_se0";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c17_data_clk: qup-i2c17-data-clk-state {
/* SDA, SCL */
pins = "gpio68", "gpio69";
function = "qup2_se1";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c18_data_clk: qup-i2c18-data-clk-state {
/* SDA, SCL */
pins = "gpio72", "gpio73";
function = "qup2_se2";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c19_data_clk: qup-i2c19-data-clk-state {
/* SDA, SCL */
pins = "gpio76", "gpio77";
function = "qup2_se3";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c20_data_clk: qup-i2c20-data-clk-state {
/* SDA, SCL */
pins = "gpio80", "gpio81";
function = "qup2_se4";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c21_data_clk: qup-i2c21-data-clk-state {
/* SDA, SCL */
pins = "gpio84", "gpio85";
function = "qup2_se5";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c22_data_clk: qup-i2c22-data-clk-state {
/* SDA, SCL */
pins = "gpio88", "gpio89";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_i2c23_data_clk: qup-i2c23-data-clk-state {
/* SDA, SCL */
pins = "gpio80", "gpio81";
function = "qup2_se7";
drive-strength = <2>;
bias-pull-up = <2200>;
};
qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio3";
function = "qup0_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi0_data_clk: qup-spi0-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio0", "gpio1", "gpio2";
function = "qup0_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi1_cs: qup-spi1-cs-state {
pins = "gpio7";
function = "qup0_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi1_data_clk: qup-spi1-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio4", "gpio5", "gpio6";
function = "qup0_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi2_cs: qup-spi2-cs-state {
pins = "gpio11";
function = "qup0_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi2_data_clk: qup-spi2-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio8", "gpio9", "gpio10";
function = "qup0_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi3_cs: qup-spi3-cs-state {
pins = "gpio15";
function = "qup0_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi3_data_clk: qup-spi3-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio12", "gpio13", "gpio14";
function = "qup0_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi4_cs: qup-spi4-cs-state {
pins = "gpio19";
function = "qup0_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi4_data_clk: qup-spi4-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio16", "gpio17", "gpio18";
function = "qup0_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi5_cs: qup-spi5-cs-state {
pins = "gpio23";
function = "qup0_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi5_data_clk: qup-spi5-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio20", "gpio21", "gpio22";
function = "qup0_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi6_cs: qup-spi6-cs-state {
pins = "gpio5";
function = "qup0_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi6_data_clk: qup-spi6-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio6", "gpio7", "gpio4";
function = "qup0_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi7_cs: qup-spi7-cs-state {
pins = "gpio13";
function = "qup0_se7";
drive-strength = <6>;
bias-disable;
};
qup_spi7_data_clk: qup-spi7-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio14", "gpio15", "gpio12";
function = "qup0_se7";
drive-strength = <6>;
bias-disable;
};
qup_spi8_cs: qup-spi8-cs-state {
pins = "gpio35";
function = "qup1_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi8_data_clk: qup-spi8-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio32", "gpio33", "gpio34";
function = "qup1_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi9_cs: qup-spi9-cs-state {
pins = "gpio39";
function = "qup1_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi9_data_clk: qup-spi9-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio36", "gpio37", "gpio38";
function = "qup1_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi10_cs: qup-spi10-cs-state {
pins = "gpio43";
function = "qup1_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi10_data_clk: qup-spi10-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio40", "gpio41", "gpio42";
function = "qup1_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi11_cs: qup-spi11-cs-state {
pins = "gpio47";
function = "qup1_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi11_data_clk: qup-spi11-data-clk-state {
pins = "gpio44", "gpio45", "gpio46";
function = "qup1_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi12_cs: qup-spi12-cs-state {
pins = "gpio51";
function = "qup1_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi12_data_clk: qup-spi12-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio48", "gpio49", "gpio50";
function = "qup1_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi13_cs: qup-spi13-cs-state {
pins = "gpio55";
function = "qup1_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi13_data_clk: qup-spi13-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio52", "gpio53", "gpio54";
function = "qup1_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi14_cs: qup-spi14-cs-state {
pins = "gpio59";
function = "qup1_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi14_data_clk: qup-spi14-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio56", "gpio57", "gpio58";
function = "qup1_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi15_cs: qup-spi15-cs-state {
pins = "gpio53";
function = "qup1_se7";
drive-strength = <6>;
bias-disable;
};
qup_spi15_data_clk: qup-spi15-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio54", "gpio55", "gpio52";
function = "qup1_se7";
drive-strength = <6>;
bias-disable;
};
qup_spi16_cs: qup-spi16-cs-state {
pins = "gpio67";
function = "qup2_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi16_data_clk: qup-spi16-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio64", "gpio65", "gpio66";
function = "qup2_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi17_cs: qup-spi17-cs-state {
pins = "gpio71";
function = "qup2_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi17_data_clk: qup-spi17-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio68", "gpio69", "gpio70";
function = "qup2_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi18_cs: qup-spi18-cs-state {
pins = "gpio75";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi18_data_clk: qup-spi18-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio72", "gpio73", "gpio74";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi19_cs: qup-spi19-cs-state {
pins = "gpio79";
function = "qup2_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi19_data_clk: qup-spi19-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio76", "gpio77", "gpio78";
function = "qup2_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi20_cs: qup-spi20-cs-state {
pins = "gpio83";
function = "qup2_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi20_data_clk: qup-spi20-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio80", "gpio81", "gpio82";
function = "qup2_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi21_cs: qup-spi21-cs-state {
pins = "gpio87";
function = "qup2_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi21_data_clk: qup-spi21-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio84", "gpio85", "gpio86";
function = "qup2_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi22_cs: qup-spi22-cs-state {
pins = "gpio91";
function = "qup2_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi22_data_clk: qup-spi22-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio88", "gpio89", "gpio90";
function = "qup2_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi23_cs: qup-spi23-cs-state {
pins = "gpio83";
function = "qup2_se7";
drive-strength = <6>;
bias-disable;
};
qup_spi23_data_clk: qup-spi23-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio80", "gpio81", "gpio82";
function = "qup2_se7";
drive-strength = <6>;
bias-disable;
};
qup_uart2_default: qup-uart2-default-state {
tx-pins {
pins = "gpio10";
function = "qup0_se2";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio11";
function = "qup0_se2";
drive-strength = <2>;
bias-disable;
};
};
qup_uart14_default: qup-uart14-default-state {
cts-pins {
pins = "gpio56";
function = "qup1_se6";
drive-strength = <2>;
bias-disable;
};
rts-pins {
pins = "gpio57";
function = "qup1_se6";
drive-strength = <2>;
bias-disable;
};
tx-pins {
pins = "gpio58";
function = "qup1_se6";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio59";
function = "qup1_se6";
drive-strength = <2>;
bias-disable;
};
};
qup_uart19_default: qup-uart19-default-state {
cts-pins {
pins = "gpio76";
function = "qup2_se3";
drive-strength = <2>;
bias-disable;
};
rts-pins {
pins = "gpio77";
function = "qup2_se3";
drive-strength = <2>;
bias-disable;
};
tx-pins {
pins = "gpio78";
function = "qup2_se3";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio79";
function = "qup2_se3";
drive-strength = <2>;
bias-disable;
};
};
qup_uart21_default: qup-uart21-default-state {
tx-pins {
pins = "gpio86";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio87";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
};
};
qup_uart22_default: qup-uart22-default-state {
tx-pins {
pins = "gpio90";
function = "qup2_se6";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio91";
function = "qup2_se6";
drive-strength = <2>;
bias-disable;
};
};
};
ctcu@10001000 {
compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu";
reg = <0x0 0x10001000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ctcu_in0: endpoint {
remote-endpoint = <&etr0_out>;
};
};
port@1 {
reg = <1>;
ctcu_in1: endpoint {
remote-endpoint = <&etr1_out>;
};
};
};
};
stm: stm@10002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x10002000 0x0 0x1000>,
<0x0 0x16280000 0x0 0x180000>;
reg-names = "stm-base",
"stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel0_in7>;
};
};
};
};
tpda@10004000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10004000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
qdss_tpda_in1: endpoint {
remote-endpoint = <&spdm_tpdm_out>;
};
};
};
out-ports {
port {
qdss_tpda_out: endpoint {
remote-endpoint = <&funnel0_in6>;
};
};
};
};
tpdm@1000f000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1000f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
spdm_tpdm_out: endpoint {
remote-endpoint = <&qdss_tpda_in1>;
};
};
};
};
funnel@10041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10041000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel0_in0: endpoint {
remote-endpoint = <&tn_ag_out>;
};
};
port@6 {
reg = <6>;
funnel0_in6: endpoint {
remote-endpoint = <&qdss_tpda_out>;
};
};
port@7 {
reg = <7>;
funnel0_in7: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint = <&aoss_funnel_in6>;
};
};
};
};
replicator@10046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x10046000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
qdss_rep_in: endpoint {
remote-endpoint = <&swao_rep_out0>;
};
};
};
out-ports {
port {
qdss_rep_out0: endpoint {
remote-endpoint = <&etr_rep_in>;
};
};
};
};
tmc@10048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10048000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
iommus = <&apps_smmu 0x00e0 0x0000>;
arm,scatter-gather;
in-ports {
port {
etr0_in: endpoint {
remote-endpoint = <&etr_rep_out0>;
};
};
};
out-ports {
port {
etr0_out: endpoint {
remote-endpoint = <&ctcu_in0>;
};
};
};
};
replicator@1004e000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x1004e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
etr_rep_in: endpoint {
remote-endpoint = <&qdss_rep_out0>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
etr_rep_out0: endpoint {
remote-endpoint = <&etr0_in>;
};
};
port@1 {
reg = <1>;
etr_rep_out1: endpoint {
remote-endpoint = <&etr1_in>;
};
};
};
};
tmc@1004f000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x1004f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
iommus = <&apps_smmu 0x0100 0x0000>;
arm,scatter-gather;
in-ports {
port {
etr1_in: endpoint {
remote-endpoint = <&etr_rep_out1>;
};
};
};
out-ports {
port {
etr1_out: endpoint {
remote-endpoint = <&ctcu_in1>;
};
};
};
};
tpdm@1102c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1102c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
gcc_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in36>;
};
};
};
};
tpdm@11180000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11180000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
cdsp_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in0>;
};
};
};
};
tpdm@11185000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11185000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_dpm_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
cdsp_dpm1_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in5>;
};
};
};
};
tpdm@11186000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11186000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_dpm_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
cdsp_dpm2_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in6>;
};
};
};
};
tpda@11188000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x11188000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cdsp_tpda_in0: endpoint {
remote-endpoint = <&cdsp_tpdm_out>;
};
};
port@1 {
reg = <1>;
cdsp_tpda_in1: endpoint {
remote-endpoint = <&cdsp_llm_tpdm_out>;
};
};
port@2 {
reg = <2>;
cdsp_tpda_in2: endpoint {
remote-endpoint = <&cdsp_llm2_tpdm_out>;
};
};
port@3 {
reg = <3>;
cdsp_tpda_in3: endpoint {
remote-endpoint = <&cdsp_cmsr_tpdm_out>;
};
};
port@4 {
reg = <4>;
cdsp_tpda_in4: endpoint {
remote-endpoint = <&cdsp_cmsr2_tpdm_out>;
};
};
port@5 {
reg = <5>;
cdsp_tpda_in5: endpoint {
remote-endpoint = <&cdsp_dpm1_tpdm_out>;
};
};
port@6 {
reg = <6>;
cdsp_tpda_in6: endpoint {
remote-endpoint = <&cdsp_dpm2_tpdm_out>;
};
};
};
out-ports {
port {
cdsp_tpda_out: endpoint {
remote-endpoint = <&cdsp_funnel_in0>;
};
};
};
};
funnel@11189000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x11189000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
cdsp_funnel_in0: endpoint {
remote-endpoint = <&cdsp_tpda_out>;
};
};
};
out-ports {
port {
cdsp_funnel_out: endpoint {
remote-endpoint = <&tn_ag_in53>;
};
};
};
};
cti@11193000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x11193000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_cdsp";
};
cti_wpss: cti@111ab000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x111ab000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_wpss";
};
tpdm@111d0000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x111d0000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_qm";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
qm_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in35>;
};
};
};
};
itnoc@11200000 {
compatible = "qcom,coresight-itnoc";
reg = <0x0 0x11200000 0x0 0x3c00>;
clocks = <&aoss_qmp>;
clock-names = "apb";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
tn_ag_in6: endpoint {
remote-endpoint = <&mm_dsb_tpdm_out>;
};
};
port@10 {
reg = <0x10>;
tn_ag_in16: endpoint {
remote-endpoint = <&east_dsb_tpdm_out>;
};
};
port@21 {
reg = <0x21>;
tn_ag_in33: endpoint {
remote-endpoint = <&west_dsb_tpdm_out>;
};
};
port@23 {
reg = <0x23>;
tn_ag_in35: endpoint {
remote-endpoint = <&qm_tpdm_out>;
};
};
port@24 {
reg = <0x24>;
tn_ag_in36: endpoint {
remote-endpoint = <&gcc_tpdm_out>;
};
};
port@32 {
reg = <0x32>;
tn_ag_in50: endpoint {
remote-endpoint = <&pcie_rscc_tpda_out>;
};
};
port@35 {
reg = <0x35>;
tn_ag_in53: endpoint {
remote-endpoint = <&cdsp_funnel_out>;
};
};
port@3f {
reg = <0x3f>;
tn_ag_in63: endpoint {
remote-endpoint = <¢er_dsb_tpdm_out>;
};
};
port@40 {
reg = <0x40>;
tn_ag_in64: endpoint {
remote-endpoint = <&ipcc_cmb_tpdm_out>;
};
};
port@41 {
reg = <0x41>;
tn_ag_in65: endpoint {
remote-endpoint = <&qrng_tpdm_out>;
};
};
port@42 {
reg = <0x42>;
tn_ag_in66: endpoint {
remote-endpoint = <&pmu_tpdm_out>;
};
};
port@43 {
reg = <0x43>;
tn_ag_in67: endpoint {
remote-endpoint = <&rdpm_west_cmb0_tpdm_out>;
};
};
port@44 {
reg = <0x44>;
tn_ag_in68: endpoint {
remote-endpoint = <&rdpm_west_cmb1_tpdm_out>;
};
};
port@45 {
reg = <0x45>;
tn_ag_in69: endpoint {
remote-endpoint = <&rdpm_west_cmb2_tpdm_out>;
};
};
port@4b {
reg = <0x4b>;
tn_ag_in75: endpoint {
remote-endpoint = <&south_dsb2_tpdm_out>;
};
};
port@52 {
reg = <0x52>;
tn_ag_in82: endpoint {
remote-endpoint = <&south_dsb_tpdm_out>;
};
};
port@53 {
reg = <0x53>;
tn_ag_in83: endpoint {
remote-endpoint = <¢er_dsb1_tpdm_out>;
};
};
};
out-ports {
port {
tn_ag_out: endpoint {
remote-endpoint = <&funnel0_in0>;
};
};
};
};
tpdm@11207000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11207000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_mm_dsb";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
mm_dsb_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in6>;
};
};
};
};
tpdm@1120b000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1120b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_east_dsb";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
east_dsb_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in16>;
};
};
};
};
tpdm@11213000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11213000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_west_dsb";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
west_dsb_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in33>;
};
};
};
};
tpdm@11219000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11219000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_center_dsb";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
center_dsb_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in63>;
};
};
};
};
tpdm@1121a000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1121a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
ipcc_cmb_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in64>;
};
};
};
};
tpdm@1121b000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1121b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_qrng";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
qrng_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in65>;
};
};
};
};
tpdm@1121c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1121c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_pmu";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
pmu_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in66>;
};
};
};
};
tpdm@1121d000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1121d000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_cx";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
rdpm_west_cmb0_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in67>;
};
};
};
};
tpdm@1121e000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1121e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_mxc";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
rdpm_west_cmb1_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in68>;
};
};
};
};
tpdm@1121f000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1121f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_mxa";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
rdpm_west_cmb2_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in69>;
};
};
};
};
tpdm@11220000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11220000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_center_dsb_1";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
center_dsb1_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in83>;
};
};
};
};
tpdm@11224000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11224000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_south2_dsb";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
south_dsb2_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in75>;
};
};
};
};
tpdm@11228000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11228000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
south_dsb_tpdm_out: endpoint {
remote-endpoint = <&tn_ag_in82>;
};
};
};
};
tpdm@11470000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11470000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_pcie_rscc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
pcie_rscc_tpdm_out: endpoint {
remote-endpoint = <&pcie_rscc_tpda_in0>;
};
};
};
};
tpda@11471000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x11471000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
pcie_rscc_tpda_in0: endpoint {
remote-endpoint = <&pcie_rscc_tpdm_out>;
};
};
};
out-ports {
port {
pcie_rscc_tpda_out: endpoint {
remote-endpoint = <&tn_ag_in50>;
};
};
};
};
tpdm@11c03000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c03000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_4";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
swao_prio4_tpdm_out: endpoint {
remote-endpoint = <&aoss_tpda_in4>;
};
};
};
};
funnel@11c04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x11c04000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@5 {
reg = <5>;
aoss_funnel_in5: endpoint {
remote-endpoint = <&aoss_tpda_out>;
};
};
port@6 {
reg = <6>;
aoss_funnel_in6: endpoint {
remote-endpoint = <&funnel0_out>;
};
};
};
out-ports {
port {
aoss_funnel_out: endpoint {
remote-endpoint = <&etf0_in>;
};
};
};
};
tmc_etf: tmc@11c05000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x11c05000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
etf0_in: endpoint {
remote-endpoint = <&aoss_funnel_out>;
};
};
};
out-ports {
port {
etf0_out: endpoint {
remote-endpoint = <&swao_rep_in>;
};
};
};
};
replicator@11c06000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x11c06000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
swao_rep_in: endpoint {
remote-endpoint = <&etf0_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
swao_rep_out0: endpoint {
remote-endpoint = <&qdss_rep_in>;
};
};
port@1 {
reg = <1>;
swao_rep_out1: endpoint {
remote-endpoint = <&eud_in>;
};
};
};
};
tpda@11c08000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x11c08000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
aoss_tpda_in0: endpoint {
remote-endpoint = <&swao_prio0_tpdm_out>;
};
};
port@1 {
reg = <1>;
aoss_tpda_in1: endpoint {
remote-endpoint = <&swao_prio1_tpdm_out>;
};
};
port@2 {
reg = <2>;
aoss_tpda_in2: endpoint {
remote-endpoint = <&swao_prio2_tpdm_out>;
};
};
port@3 {
reg = <3>;
aoss_tpda_in3: endpoint {
remote-endpoint = <&swao_prio3_tpdm_out>;
};
};
port@4 {
reg = <4>;
aoss_tpda_in4: endpoint {
remote-endpoint = <&swao_prio4_tpdm_out>;
};
};
port@5 {
reg = <5>;
aoss_tpda_in5: endpoint {
remote-endpoint = <&swao_tpdm_out>;
};
};
};
out-ports {
port {
aoss_tpda_out: endpoint {
remote-endpoint = <&aoss_funnel_in5>;
};
};
};
};
tpdm@11c09000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c09000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
swao_prio0_tpdm_out: endpoint {
remote-endpoint = <&aoss_tpda_in0>;
};
};
};
};
tpdm@11c0a000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c0a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
swao_prio1_tpdm_out: endpoint {
remote-endpoint = <&aoss_tpda_in1>;
};
};
};
};
tpdm@11c0b000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c0b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
swao_prio2_tpdm_out: endpoint {
remote-endpoint = <&aoss_tpda_in2>;
};
};
};
};
tpdm@11c0c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c0c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
swao_prio3_tpdm_out: endpoint {
remote-endpoint = <&aoss_tpda_in3>;
};
};
};
};
tpdm@11c0d000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x11c0d000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
swao_tpdm_out: endpoint {
remote-endpoint = <&aoss_tpda_in5>;
};
};
};
};
sram@14680000 {
compatible = "qcom,glymur-imem", "mmio-sram";
reg = <0x0 0x14680000 0x0 0x2c000>;
ranges = <0 0 0x14680000 0x2c000>;
no-memory-wc;
#address-cells = <1>;
#size-cells = <1>;
pil-sram@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,glymur-smmu-500",
"qcom,smmu-500",
"arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
pcie_smmu: iommu@15480000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x15480000 0x0 0x20000>;
interrupts = <GIC_ESPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
#iommu-cells = <1>;
};
intc: interrupt-controller@17000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17000000 0x0 0x10000>,
<0x0 0x17080000 0x0 0x480000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
interrupt-controller;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic_its: msi-controller@17040000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x17040000 0x0 0x40000>;
msi-controller;
#msi-cells = <1>;
};
};
watchdog@17600000 {
compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt";
reg = <0x0 0x17600000 0x0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
pdp0_mbox: mailbox@17610000 {
compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
timer@17810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17810000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x0 0x20000000>;
frame@17811000 {
reg = <0x0 0x17811000 0x1000>,
<0x0 0x17812000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@17813000 {
reg = <0x0 0x17813000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@17815000 {
reg = <0x0 0x17815000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@17817000 {
reg = <0x0 0x17817000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@17819000 {
reg = <0x0 0x17819000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@1781b000 {
reg = <0x0 0x1781b000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@1781d000 {
reg = <0x0 0x1781d000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
apps_rsc: rsc@18900000 {
compatible = "qcom,rpmh-rsc";
label = "apps_rsc";
reg = <0x0 0x18900000 0x0 0x10000>,
<0x0 0x18910000 0x0 0x10000>,
<0x0 0x18920000 0x0 0x10000>;
reg-names = "drv-0",
"drv-1",
"drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
power-domains = <&system_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller {
compatible = "qcom,glymur-rpmh-clk";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmhpd: power-controller {
compatible = "qcom,glymur-rpmhpd";
operating-points-v2 = <&rpmhpd_opp_table>;
#power-domain-cells = <1>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp-16 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp-48 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs_d2: opp-52 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
};
rpmhpd_opp_low_svs_d1: opp-56 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
};
rpmhpd_opp_low_svs_d0: opp-60 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
};
rpmhpd_opp_low_svs: opp-64 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_low_svs_l1: opp-80 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
};
rpmhpd_opp_svs: opp-128 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l0: opp-144 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
};
rpmhpd_opp_svs_l1: opp-192 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp-256 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp-320 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp-336 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp-384 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp-416 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
};
nsi_noc: interconnect@1d600000 {
compatible = "qcom,glymur-nsinoc";
reg = <0x0 0x1d600000 0x0 0x14080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
oobm_ss_noc: interconnect@1f300000 {
compatible = "qcom,glymur-oobm-ss-noc";
reg = <0x0 0x1f300000 0x0 0x49a00>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
system-cache-controller@21800000 {
compatible = "qcom,glymur-llcc";
reg = <0x0 0x21800000 0x0 0x100000>,
<0x0 0x21a00000 0x0 0x100000>,
<0x0 0x21c00000 0x0 0x100000>,
<0x0 0x21e00000 0x0 0x100000>,
<0x0 0x22800000 0x0 0x100000>,
<0x0 0x22a00000 0x0 0x100000>,
<0x0 0x22c00000 0x0 0x100000>,
<0x0 0x22e00000 0x0 0x100000>,
<0x0 0x23800000 0x0 0x100000>,
<0x0 0x23a00000 0x0 0x100000>,
<0x0 0x23c00000 0x0 0x100000>,
<0x0 0x23e00000 0x0 0x100000>,
<0x0 0x20400000 0x0 0x100000>,
<0x0 0x20600000 0x0 0x100000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
"llcc4_base",
"llcc5_base",
"llcc6_base",
"llcc7_base",
"llcc8_base",
"llcc9_base",
"llcc10_base",
"llcc11_base",
"llcc_broadcast_base",
"llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas";
reg = <0x0 0x32300000 0x0 0x10000>;
iommus = <&apps_smmu 0x2400 0x400>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_NSP>;
power-domain-names = "cx",
"mxc",
"nsp";
memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_MPROC_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <5>;
label = "cdsp";
fastrpc {
compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x2401 0x440>,
<&apps_smmu 0x1961 0x0>,
<&apps_smmu 0x19c1 0x0>;
dma-coherent;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x2402 0x440>,
<&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x19c2 0x0>;
dma-coherent;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x2403 0x440>,
<&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x19c3 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x2404 0x440>,
<&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x19c4 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x2405 0x440>,
<&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x19c5 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x2406 0x440>,
<&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x19c6 0x0>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x2407 0x440>,
<&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x19c7 0x0>;
dma-coherent;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x2408 0x440>,
<&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x19c8 0x0>;
dma-coherent;
};
/* note: compute-cb@9 is secure */
compute-cb@10 {
compatible = "qcom,fastrpc-compute-cb";
reg = <10>;
iommus = <&apps_smmu 0x240c 0x440>,
<&apps_smmu 0x196c 0x0>,
<&apps_smmu 0x19cc 0x0>;
dma-coherent;
};
compute-cb@11 {
compatible = "qcom,fastrpc-compute-cb";
reg = <11>;
iommus = <&apps_smmu 0x240d 0x440>,
<&apps_smmu 0x196d 0x0>,
<&apps_smmu 0x19cd 0x0>;
dma-coherent;
};
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <12>;
iommus = <&apps_smmu 0x240e 0x440>,
<&apps_smmu 0x196e 0x0>,
<&apps_smmu 0x19ce 0x0>;
dma-coherent;
};
};
};
};
nsp_noc: interconnect@320c0000 {
compatible = "qcom,glymur-nsp-noc";
reg = <0x0 0x320c0000 0x0 0x21280>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
qfprom: efuse@361c8000 {
compatible = "qcom,glymur-qfprom", "qcom,qfprom";
reg = <0x0 0x361c8000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu-speed-bin@138 {
reg = <0x138 0x2>;
bits = <0 9>;
};
};
imem: sram@81e08600 {
compatible = "mmio-sram";
reg = <0x0 0x81e08600 0x0 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81e08600 0x300>;
cpu_scp_lpri0: scp-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x180>;
};
cpu_scp_lpri1: scp-sram-section@180 {
compatible = "arm,scmi-shmem";
reg = <0x180 0x180>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
thermal_zones: thermal-zones {
aoss-0-thermal {
thermal-sensors = <&tsens0 0>;
trips {
aoss-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-0-0-thermal {
thermal-sensors = <&tsens0 1>;
trips {
cpu-0-0-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-0-1-thermal {
thermal-sensors = <&tsens0 2>;
trips {
cpu-0-0-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-1-0-thermal {
thermal-sensors = <&tsens0 3>;
trips {
cpu-0-1-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-1-1-thermal {
thermal-sensors = <&tsens0 4>;
trips {
cpu-0-1-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-2-0-thermal {
thermal-sensors = <&tsens0 5>;
trips {
cpu-0-2-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-2-1-thermal {
thermal-sensors = <&tsens0 6>;
trips {
cpu-0-2-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-3-0-thermal {
thermal-sensors = <&tsens0 7>;
trips {
cpu-0-3-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-3-1-thermal {
thermal-sensors = <&tsens0 8>;
trips {
cpu-0-3-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-4-0-thermal {
thermal-sensors = <&tsens0 9>;
trips {
cpu-0-4-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-4-1-thermal {
thermal-sensors = <&tsens0 10>;
trips {
cpu-0-4-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-5-0-thermal {
thermal-sensors = <&tsens0 11>;
trips {
cpu-0-5-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-0-5-1-thermal {
thermal-sensors = <&tsens0 12>;
trips {
cpu-0-5-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss-1-thermal {
thermal-sensors = <&tsens1 0>;
trips {
aoss-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpullc-0-0-thermal {
thermal-sensors = <&tsens1 1>;
trips {
cpullc-0-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpullc-0-1-thermal {
thermal-sensors = <&tsens1 2>;
trips {
cpullc-0-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-0-0-thermal {
thermal-sensors = <&tsens1 3>;
trips {
qmx-0-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-0-1-thermal {
thermal-sensors = <&tsens1 4>;
trips {
qmx-0-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-0-2-thermal {
thermal-sensors = <&tsens1 5>;
trips {
qmx-0-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
ddr-0-thermal {
thermal-sensors = <&tsens1 6>;
trips {
ddr-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_video_0: video-0-thermal {
thermal-sensors = <&tsens1 7>;
trips {
video-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_video_1: video-1-thermal {
thermal-sensors = <&tsens1 8>;
trips {
video-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss-2-thermal {
thermal-sensors = <&tsens2 0>;
trips {
aoss-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-0-0-thermal {
thermal-sensors = <&tsens2 1>;
trips {
cpu-1-0-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-0-1-thermal {
thermal-sensors = <&tsens2 2>;
trips {
cpu-1-0-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-1-0-thermal {
thermal-sensors = <&tsens2 3>;
trips {
cpu-1-1-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-1-1-thermal {
thermal-sensors = <&tsens2 4>;
trips {
cpu-1-1-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-2-0-thermal {
thermal-sensors = <&tsens2 5>;
trips {
cpu-1-2-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-2-1-thermal {
thermal-sensors = <&tsens2 6>;
trips {
cpu-1-2-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-3-0-thermal {
thermal-sensors = <&tsens2 7>;
trips {
cpu-1-3-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-3-1-thermal {
thermal-sensors = <&tsens2 8>;
trips {
cpu-1-3-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-4-0-thermal {
thermal-sensors = <&tsens2 9>;
trips {
cpu-1-4-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-4-1-thermal {
thermal-sensors = <&tsens2 10>;
trips {
cpu-1-4-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-5-0-thermal {
thermal-sensors = <&tsens2 11>;
trips {
cpu-1-5-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-1-5-1-thermal {
thermal-sensors = <&tsens2 12>;
trips {
cpu-1-5-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss-3-thermal {
thermal-sensors = <&tsens3 0>;
trips {
aoss-3-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpullc-1-0-thermal {
thermal-sensors = <&tsens3 1>;
trips {
cpullc-1-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpullc-1-1-thermal {
thermal-sensors = <&tsens3 2>;
trips {
cpullc-1-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-1-0-thermal {
thermal-sensors = <&tsens3 3>;
trips {
qmx-1-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-1-1-thermal {
thermal-sensors = <&tsens3 4>;
trips {
qmx-1-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-1-2-thermal {
thermal-sensors = <&tsens3 5>;
trips {
qmx-1-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-1-3-thermal {
thermal-sensors = <&tsens3 6>;
trips {
qmx-1-3-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
qmx-1-4-thermal {
thermal-sensors = <&tsens3 7>;
trips {
qmx-1-4-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss-4-thermal {
thermal-sensors = <&tsens4 0>;
trips {
aoss-4-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_0_0: cpu-2-0-0-thermal {
thermal-sensors = <&tsens4 1>;
trips {
cpu-2-0-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_0_1: cpu-2-0-1-thermal {
thermal-sensors = <&tsens4 2>;
trips {
cpu-2-0-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_1_0: cpu-2-1-0-thermal {
thermal-sensors = <&tsens4 3>;
trips {
cpu-2-1-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_1_1: cpu-2-1-1-thermal {
thermal-sensors = <&tsens4 4>;
trips {
cpu-2-1-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_2_0: cpu-2-2-0-thermal {
thermal-sensors = <&tsens4 5>;
trips {
cpu-2-2-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_2_1: cpu-2-2-1-thermal {
thermal-sensors = <&tsens4 6>;
trips {
cpu-2-2-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_3_0: cpu-2-3-0-thermal {
thermal-sensors = <&tsens4 7>;
trips {
cpu-2-3-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_3_1: cpu-2-3-1-thermal {
thermal-sensors = <&tsens4 8>;
trips {
cpu-2-3-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_4_0: cpu-2-4-0-thermal {
thermal-sensors = <&tsens4 9>;
trips {
cpu-2-4-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_4_1: cpu-2-4-1-thermal {
thermal-sensors = <&tsens4 10>;
trips {
cpu-2-4-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_5_0: cpu-2-5-0-thermal {
thermal-sensors = <&tsens4 11>;
trips {
cpu-2-5-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpu_2_5_1: cpu-2-5-1-thermal {
thermal-sensors = <&tsens4 12>;
trips {
cpu-2-5-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss-5-thermal {
thermal-sensors = <&tsens5 0>;
trips {
aoss-5-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpullc_2_0: cpullc-2-0-thermal {
thermal-sensors = <&tsens5 1>;
trips {
cpullc-2-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_cpuillc_2_1: cpuillc-2-1-thermal {
thermal-sensors = <&tsens5 2>;
trips {
cpullc-2-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_qmx_2_0: qmx-2-0-thermal {
thermal-sensors = <&tsens5 3>;
trips {
qmx-2-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_qmx_2_1: qmx-2-1-thermal {
thermal-sensors = <&tsens5 4>;
trips {
qmx-2-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_qmx_2_2: qmx-2-2-thermal {
thermal-sensors = <&tsens5 5>;
trips {
qmx-2-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_qmx_2_3: qmx-2-3-thermal {
thermal-sensors = <&tsens5 6>;
trips {
qmx-2-3-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_qmx_2_4: qmx-2-4-thermal {
thermal-sensors = <&tsens5 7>;
trips {
qmx-2-4-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_aoss_6: aoss-6-thermal {
thermal-sensors = <&tsens6 0>;
trips {
aoss-6-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphvx_0: nsphvx-0-thermal {
thermal-sensors = <&tsens6 1>;
trips {
nsphvx-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphvx_1: nsphvx-1-thermal {
thermal-sensors = <&tsens6 2>;
trips {
nsphvx-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphvx_2: nsphvx-2-thermal {
thermal-sensors = <&tsens6 3>;
trips {
nsphvx-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphvx_3: nsphvx-3-thermal {
thermal-sensors = <&tsens6 4>;
trips {
nsphvx-3-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphmx_0: nsphmx-0-thermal {
thermal-sensors = <&tsens6 5>;
trips {
nsphmx-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphmx_1: nsphmx-1-thermal {
thermal-sensors = <&tsens6 6>;
trips {
nsphmx-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphmx_2: nsphmx-2-thermal {
thermal-sensors = <&tsens6 7>;
trips {
nsphmx-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_nsphmx_3: nsphmx-3-thermal {
thermal-sensors = <&tsens6 8>;
trips {
nsphmx-3-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_camera_0: camera-0-thermal {
thermal-sensors = <&tsens6 9>;
trips {
camera-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_camera_1: camera-1-thermal {
thermal-sensors = <&tsens6 10>;
trips {
camera-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_ddr_1: ddr-1-thermal {
thermal-sensors = <&tsens6 11>;
trips {
ddr-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_ddr_2: ddr-2-thermal {
thermal-sensors = <&tsens6 12>;
trips {
ddr-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_aoss_7: aoss-7-thermal {
thermal-sensors = <&tsens7 0>;
trips {
aoss-7-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_0_0: gpu-0-0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 1>;
cooling-maps {
map0 {
trip = <&gpu00_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu00_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-0-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_0_1: gpu-0-1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 2>;
cooling-maps {
map0 {
trip = <&gpu01_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu01_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-0-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_0_2: gpu-0-2-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 3>;
cooling-maps {
map0 {
trip = <&gpu02_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu02_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-0-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_1_0: gpu-1-0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 4>;
cooling-maps {
map0 {
trip = <&gpu10_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu10_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-1-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_1_1: gpu-1-1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 5>;
cooling-maps {
map0 {
trip = <&gpu11_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu11_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-1-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_1_2: gpu-1-2-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 6>;
cooling-maps {
map0 {
trip = <&gpu12_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu12_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-1-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_2_0: gpu-2-0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 7>;
cooling-maps {
map0 {
trip = <&gpu20_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu20_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-2-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_2_1: gpu-2-1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 8>;
cooling-maps {
map0 {
trip = <&gpu21_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu21_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-2-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_2_2: gpu-2-2-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 9>;
cooling-maps {
map0 {
trip = <&gpu22_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu22_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-2-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_3_0: gpu-3-0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 10>;
cooling-maps {
map0 {
trip = <&gpu30_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu30_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-3-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_3_1: gpu-3-1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 11>;
cooling-maps {
map0 {
trip = <&gpu31_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu31_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-3-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpu_3_2: gpu-3-2-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 12>;
cooling-maps {
map0 {
trip = <&gpu32_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu32_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpu-3-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpuss_0: gpuss-0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 13>;
cooling-maps {
map0 {
trip = <&gpuss0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpuss0_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpuss-0-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
thermal_gpuss_1: gpuss-1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&tsens7 14>;
cooling-maps {
map0 {
trip = <&gpuss1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpuss1_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
gpuss-1-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
out-ports {
port {
cdsp_llm_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in1>;
};
};
};
};
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
out-ports {
port {
cdsp_llm2_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in2>;
};
};
};
};
tpdm-cdsp-cmsr {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
qcom,dsb-element-bits = <32>;
out-ports {
port {
cdsp_cmsr_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in3>;
};
};
};
};
tpdm-cdsp-cmsr2 {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
qcom,dsb-element-bits = <32>;
out-ports {
port {
cdsp_cmsr2_tpdm_out: endpoint {
remote-endpoint = <&cdsp_tpda_in4>;
};
};
};
};
};
