Open Menu / Documentation / devicetree / bindings / pci / eswin,pcie.yaml 
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ESWIN PCIe Root Complex

maintainers:
  - Yu Ning <ningyu@eswincomputing.com>
  - Senchuan Zhang <zhangsenchuan@eswincomputing.com>
  - Yanghui Ou <ouyanghui@eswincomputing.com>

description:
  ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP.

properties:
  compatible:
    const: eswin,eic7700-pcie

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: dbi
      - const: config
      - const: elbi

  ranges:
    maxItems: 3

  '#interrupt-cells':
    const: 1

  interrupt-names:
    items:
      - const: msi
      - const: inta
      - const: intb
      - const: intc
      - const: intd

  interrupt-map:
    maxItems: 4

  interrupt-map-mask:
    items:
      - const: 0
      - const: 0
      - const: 0
      - const: 7

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: mstr
      - const: dbi
      - const: phy_reg
      - const: aux

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: dbi
      - const: pwr

patternProperties:
  "^pcie@":
    type: object
    $ref: /schemas/pci/pci-pci-bridge.yaml#

    properties:
      reg:
        maxItems: 1

      num-lanes:
        maximum: 4

      resets:
        maxItems: 1

      reset-names:
        items:
          - const: perst

    required:
      - reg
      - ranges
      - num-lanes
      - resets
      - reset-names

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - ranges
  - interrupts
  - interrupt-names
  - interrupt-map-mask
  - interrupt-map
  - '#interrupt-cells'
  - clocks
  - clock-names
  - resets
  - reset-names

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

unevaluatedProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@54000000 {
            compatible = "eswin,eic7700-pcie";
            reg = <0x0 0x54000000 0x0 0x4000000>,
                  <0x0 0x40000000 0x0 0x800000>,
                  <0x0 0x50000000 0x0 0x100000>;
            reg-names = "dbi", "config", "elbi";
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>,
                     <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>,
                     <0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>;
            bus-range = <0x00 0xff>;
            clocks = <&clock 144>,
                     <&clock 145>,
                     <&clock 146>,
                     <&clock 147>;
            clock-names = "mstr", "dbi", "phy_reg", "aux";
            resets = <&reset 97>,
                     <&reset 98>;
            reset-names = "dbi", "pwr";
            interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
            interrupt-names = "msi", "inta", "intb", "intc", "intd";
            interrupt-parent = <&plic>;
            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
            interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>,
                            <0x0 0x0 0x0 0x2 &plic 180>,
                            <0x0 0x0 0x0 0x3 &plic 181>,
                            <0x0 0x0 0x0 0x4 &plic 182>;
            device_type = "pci";
            pcie@0 {
                reg = <0x0 0x0 0x0 0x0 0x0>;
                #address-cells = <3>;
                #size-cells = <2>;
                ranges;
                device_type = "pci";
                num-lanes = <4>;
                resets = <&reset 99>;
                reset-names = "perst";
            };
        };
    };