# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments AM65x Display Subsystem
maintainers:
- Jyri Sarha <jsarha@ti.com>
- Tomi Valkeinen <tomi.valkeinen@ti.com>
description: |
The AM625 and AM65x TI Keystone Display SubSystem has two output
ports and two video planes. In AM65x DSS, the first video port
supports 1 OLDI TX and in AM625 DSS, the first video port output is
internally routed to 2 OLDI TXes. The second video port supports DPI
format. The first plane is full video plane with all features and the
second is a "lite plane" without scaling support.
The AM62L display subsystem has a single output port which supports DPI
format but it only supports single video "lite plane" which does not support
scaling. The output port is routed to SoC boundary via DPI interface and same
DPI signals are also routed internally to DSI Tx controller present within the
SoC. Due to clocking limitations only one of the interface i.e. either DSI or
DPI can be used at once.
properties:
compatible:
enum:
- ti,am625-dss
- ti,am62a7-dss
- ti,am62l-dss
- ti,am65x-dss
reg:
description:
Addresses to each DSS memory region described in the SoC's TRM.
oneOf:
- items:
- description: common DSS register area
- description: VIDL1 light video plane
- description: VID video plane
- description: OVR1 overlay manager for vp1
- description: OVR2 overlay manager for vp2
- description: VP1 video port 1
- description: VP2 video port 2
- description: common1 DSS register area
- items:
- description: common DSS register area
- description: VIDL1 light video plane
- description: OVR1 overlay manager for vp1
- description: VP1 video port 1
- description: common1 DSS register area
reg-names:
oneOf:
- items:
- const: common
- const: vidl1
- const: vid
- const: ovr1
- const: ovr2
- const: vp1
- const: vp2
- const: common1
- items:
- const: common
- const: vidl1
- const: ovr1
- const: vp1
- const: common1
clocks:
minItems: 2
items:
- description: fck DSS functional clock
- description: vp1 Video Port 1 pixel clock
- description: vp2 Video Port 2 pixel clock
clock-names:
minItems: 2
items:
- const: fck
- const: vp1
- const: vp2
assigned-clocks:
minItems: 1
maxItems: 3
assigned-clock-parents:
minItems: 1
maxItems: 3
interrupts:
maxItems: 1
power-domains:
maxItems: 1
description: phandle to the associated power domain
dma-coherent: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
For AM65x DSS, the OLDI output port node from video port 1.
For AM625 DSS, the internal DPI output port node from video
port 1.
For AM62A7 DSS, the port is tied off inside the SoC.
For AM62L DSS, the DSS DPI output port node from video port 1
or DSI Tx controller node connected to video port 1.
properties:
endpoint@0:
$ref: /schemas/graph.yaml#/properties/endpoint
description:
For AM625 DSS, VP Connection to OLDI0.
For AM65X DSS, OLDI output from the SoC.
endpoint@1:
$ref: /schemas/graph.yaml#/properties/endpoint
description:
For AM625 DSS, VP Connection to OLDI1.
anyOf:
- required:
- endpoint
- required:
- endpoint@0
- endpoint@1
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
The DSS DPI output port node from video port 2
ti,am65x-oldi-io-ctrl:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to syscon device node mapping OLDI IO_CTRL registers.
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
interface to work.
max-memory-bandwidth:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Input memory (from main memory to dispc) bandwidth limit in
bytes per second
oldi-transmitters:
description:
Child node under the DSS, to describe all the OLDI transmitters connected
to the DSS videoports.
type: object
additionalProperties: false
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
'^oldi@[0-1]$':
$ref: ti,am625-oldi.yaml#
description: OLDI transmitters connected to the DSS VPs
allOf:
- if:
properties:
compatible:
contains:
const: ti,am62a7-dss
then:
properties:
oldi-transmitters: false
ports:
properties:
port@0: false
- if:
properties:
compatible:
contains:
const: ti,am62l-dss
then:
properties:
ports:
properties:
port@1: false
reg:
maxItems: 5
reg-names:
maxItems: 5
clocks:
maxItems: 2
clock-names:
maxItems: 2
else:
properties:
reg:
minItems: 8
reg-names:
minItems: 8
clocks:
minItems: 3
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- ti,am62l-dss
- ti,am65x-dss
then:
properties:
oldi-transmitters: false
ports:
properties:
port@0:
properties:
endpoint@1: false
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interrupts
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x04a00000 0x1000>, /* common */
<0x04a02000 0x1000>, /* vidl1 */
<0x04a06000 0x1000>, /* vid */
<0x04a07000 0x1000>, /* ovr1 */
<0x04a08000 0x1000>, /* ovr2 */
<0x04a0a000 0x1000>, /* vp1 */
<0x04a0b000 0x1000>, /* vp2 */
<0x04a01000 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2", "common1";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 67 1>,
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
oldi_out0: endpoint {
remote-endpoint = <&lcd_in0>;
};
};
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
dss1: dss@30200000 {
compatible = "ti,am625-dss";
reg = <0x00 0x30200000 0x00 0x1000>, /* common */
<0x00 0x30202000 0x00 0x1000>, /* vidl1 */
<0x00 0x30206000 0x00 0x1000>, /* vid */
<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
<0x00 0x3020a000 0x00 0x1000>, /* vp1 */
<0x00 0x3020b000 0x00 0x1000>, /* vp2 */
<0x00 0x30201000 0x00 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2", "common1";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&vp1_clock>,
<&k3_clks 186 2>;
clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
oldi-transmitters {
#address-cells = <1>;
#size-cells = <0>;
oldi0: oldi@0 {
reg = <0>;
clocks = <&k3_clks 186 0>;
clock-names = "serial";
ti,companion-oldi = <&oldi1>;
ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
oldi0_in: endpoint {
remote-endpoint = <&dpi0_out0>;
};
};
port@1 {
reg = <1>;
oldi0_out: endpoint {
remote-endpoint = <&panel_in0>;
};
};
};
};
oldi1: oldi@1 {
reg = <1>;
clocks = <&k3_clks 186 0>;
clock-names = "serial";
ti,secondary-oldi;
ti,companion-oldi = <&oldi0>;
ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
oldi1_in: endpoint {
remote-endpoint = <&dpi0_out1>;
};
};
port@1 {
reg = <1>;
oldi1_out: endpoint {
remote-endpoint = <&panel_in1>;
};
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
dpi0_out0: endpoint@0 {
reg = <0>;
remote-endpoint = <&oldi0_in>;
};
dpi0_out1: endpoint@1 {
reg = <1>;
remote-endpoint = <&oldi1_in>;
};
};
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&hdmi_bridge>;
};
};
};
};
};
