Open Menu / Documentation / devicetree / bindings / crypto / qcom,inline-crypto-engine.yaml 
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

properties:
  compatible:
    items:
      - enum:
          - qcom,eliza-inline-crypto-engine
          - qcom,hawi-inline-crypto-engine
          - qcom,kaanapali-inline-crypto-engine
          - qcom,maili-inline-crypto-engine
          - qcom,milos-inline-crypto-engine
          - qcom,nord-inline-crypto-engine
          - qcom,qcs8300-inline-crypto-engine
          - qcom,sa8775p-inline-crypto-engine
          - qcom,sc7180-inline-crypto-engine
          - qcom,sc7280-inline-crypto-engine
          - qcom,shikra-inline-crypto-engine
          - qcom,sm8450-inline-crypto-engine
          - qcom,sm8550-inline-crypto-engine
          - qcom,sm8650-inline-crypto-engine
          - qcom,sm8750-inline-crypto-engine
          - qcom,x1e80100-inline-crypto-engine
      - const: qcom,inline-crypto-engine

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: iface

  power-domains:
    maxItems: 1

  operating-points-v2: true

  opp-table:
    type: object

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

# Do not extend the list.
# Legacy SoCs are allowed for single clock.
# New SoCs must provide both clocks and power domains.
allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - qcom,kaanapali-inline-crypto-engine
                - qcom,qcs8300-inline-crypto-engine
                - qcom,sa8775p-inline-crypto-engine
                - qcom,sc7180-inline-crypto-engine
                - qcom,sc7280-inline-crypto-engine
                - qcom,sm8450-inline-crypto-engine
                - qcom,sm8550-inline-crypto-engine
                - qcom,sm8650-inline-crypto-engine
                - qcom,sm8750-inline-crypto-engine

    then:
      required:
        - power-domains
        - clock-names
      properties:
        clocks:
          minItems: 2
        clock-names:
          minItems: 2

examples:
  - |
    #include <dt-bindings/clock/qcom,sm8550-gcc.h>

    crypto@1d88000 {
      compatible = "qcom,sm8550-inline-crypto-engine",
                   "qcom,inline-crypto-engine";
      reg = <0x01d88000 0x8000>;
      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
               <&gcc GCC_UFS_PHY_AHB_CLK>;
      clock-names = "core",
                    "iface";
      power-domains = <&gcc UFS_PHY_GDSC>;

      operating-points-v2 = <&ice_opp_table>;

      ice_opp_table: opp-table {
        compatible = "operating-points-v2";

        opp-100000000 {
          opp-hz = /bits/ 64 <100000000>;
          required-opps = <&rpmhpd_opp_low_svs>;
        };

        opp-201500000 {
          opp-hz = /bits/ 64 <201500000>;
          required-opps = <&rpmhpd_opp_svs_l1>;
        };

        opp-403000000 {
          opp-hz = /bits/ 64 <403000000>;
          required-opps = <&rpmhpd_opp_nom>;
        };
      };
    };
...