Open Menu / Documentation / devicetree / bindings / clock / qcom,hawi-gpucc.yaml 
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,hawi-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller on Hawi

maintainers:
  - Dongfang Zhao <dongfang.zhao@oss.qualcomm.com>

description: |
  Qualcomm graphics clock control module provides the clocks, resets and power
  domains on Qualcomm SoCs.

  See also: include/dt-bindings/clock/qcom,hawi-gpucc.h

properties:
  compatible:
    enum:
      - qcom,hawi-gpucc
      - qcom,maili-gpucc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 main branch source
      - description: GPLL0 div branch source

  power-domains:
    items:
      - description: A phandle to the MX power-domain
      - description: A phandle to the CX power-domain
      - description: A phandle to the GMXC power-domain

  required-opps:
    items:
      - description: MX performance points
      - description: CX performance points
      - description: GMXC performance points

required:
  - compatible
  - clocks
  - power-domains
  - required-opps
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,hawi-gcc.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        clock-controller@3d90000 {
            compatible = "qcom,hawi-gpucc";
            reg = <0x0 0x03d90000 0x0 0x9800>;
            clocks = <&bi_tcxo_div2>,
                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
            power-domains = <&rpmhpd RPMHPD_MX>,
                            <&rpmhpd RPMHPD_CX>,
                            <&rpmhpd RPMHPD_GMXC>;
            required-opps = <&rpmhpd_opp_low_svs>,
                            <&rpmhpd_opp_low_svs>,
                            <&rpmhpd_opp_low_svs_d3>;
            #clock-cells = <1>;
            #reset-cells = <1>;
            #power-domain-cells = <1>;
        };
    };
...