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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_ddi.c dp_tp_ctl_reg() -> tgl_dp_tp_transcoder()

Type Parameter Key Value
BUF_SIZE 0 crtc_state (-1),4,24,64,168-s32max
BUF_SIZE 0 crtc_state (-1),4,24,64,168-s32max
DATA_SOURCE 0 crtc_state $1
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 crtc_state->cgm_mode 0-u32max
HOST_DATA 0 crtc_state->csc_mode 0-u32max
HOST_DATA 0 crtc_state->dp_m2_n2.data_m 0-16777215
HOST_DATA 0 crtc_state->dp_m2_n2.data_n 0-16777215
HOST_DATA 0 crtc_state->dp_m2_n2.link_m 0-16777215
HOST_DATA 0 crtc_state->dp_m2_n2.link_n 0-16777215
HOST_DATA 0 crtc_state->dp_m_n.data_m 0-16777215
HOST_DATA 0 crtc_state->dp_m_n.data_n 0-16777215
HOST_DATA 0 crtc_state->dp_m_n.link_m 0-16777215
HOST_DATA 0 crtc_state->dp_m_n.link_n 0-16777215
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.ebb0 0,256-65280[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.ebb4 0,8192[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pcsdw12 0-95[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll0 0-255[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll1 0,256-3840[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll10 0,1024-134233088[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll2 0-4194303[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll3 0,65536[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll6 0-466703[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll8 0-1023[c]
HOST_DATA 0 crtc_state->dpll_hw_state.bxt.pll9 0,2-14[c]
HOST_DATA 0 crtc_state->dpll_hw_state.cx0pll.ssc_enabled 0-1
HOST_DATA 0 crtc_state->dpll_hw_state.hsw.spll 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.hsw.wrpll 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.i9xx.dpll 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.i9xx.dpll_md 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.i9xx.fp0 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.i9xx.fp1 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.cfgcr0 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.cfgcr1 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.div0 0,33554432-234881024[c]
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_clktop2_coreclkctl1 0,256-65280[c]
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_clktop2_hsclkctl 0,256-130816[c]
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_bias 0-u32max[c]
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_div0 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_div1 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_frac_lock 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_lf 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_ssc 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_pll_tdc_coldst_bias 0-u32max[c]
HOST_DATA 0 crtc_state->dpll_hw_state.icl.mg_refclkin_ctl 0,256-1792[c]
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_cp 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_div 0-s32max[c]
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_div2 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_fracn1 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_fracn2 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_sscen 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.mpllb_sscstep 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.mpllb.ref_control 0,134217728-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.skl.cfgcr1 0-u32max
HOST_DATA 0 crtc_state->dpll_hw_state.skl.cfgcr2 0-u32max
HOST_DATA 0 crtc_state->dsc.config.block_pred_enable 0-1
HOST_DATA 0 crtc_state->dsc.config.convert_rgb 0-1
HOST_DATA 0 crtc_state->dsc.config.native_422 0-1
HOST_DATA 0 crtc_state->dsc.config.simple_422 0-1
HOST_DATA 0 crtc_state->dsc.config.vbr_enable 0-1
HOST_DATA 0 crtc_state->dsi_pll.ctrl 0-u32max
HOST_DATA 0 crtc_state->dsi_pll.div 0-u32max
HOST_DATA 0 crtc_state->enhanced_framing 0-1
HOST_DATA 0 crtc_state->fdi_lanes 2-8[c]
HOST_DATA 0 crtc_state->fdi_m_n.data_m 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.data_n 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.link_m 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.link_n 0-16777215
HOST_DATA 0 crtc_state->fec_enable 0-1
HOST_DATA 0 crtc_state->gamma_mode 0-u32max
HOST_DATA 0 crtc_state->gmch_pfit.control 0-u32max[c]
HOST_DATA 0 crtc_state->gmch_pfit.lvds_border_bits 0,32768
HOST_DATA 0 crtc_state->gmch_pfit.pgm_ratios 0-u32max
HOST_DATA 0 crtc_state->has_audio 0-1
HOST_DATA 0 crtc_state->hw.adjusted_mode.clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_clock 0-s32max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.adjusted_mode.hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.background_color 0-1073741823
HOST_DATA 0 crtc_state->hw.mode.clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hblank_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hblank_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.mode.hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hblank_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hblank_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.pipe_mode.hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.htotal 0-u16max[c]
HOST_DATA 0 crtc_state->infoframes.enable 0-u32max[c]
HOST_DATA 0 crtc_state->infoframes.gcp 0-u32max
HOST_DATA 0 crtc_state->ips_enabled 0-1
HOST_DATA 0 crtc_state->lane_count 1-8[c]
HOST_DATA 0 crtc_state->min_hblank 0-s32max
HOST_DATA 0 crtc_state->mst_master_transcoder 0-s32max[c]
HOST_DATA 0 crtc_state->pixel_multiplier 1-8[c]
HOST_DATA 0 crtc_state->pixel_rate 0-u32max[c]
HOST_DATA 0 crtc_state->port_clock 0-s32max[c]
HOST_DATA 0 crtc_state->set_context_latency 0-u16max
HOST_DATA 0 crtc_state->splitter.pixel_overlap 0-255[c]
HOST_DATA 0 crtc_state->vrr.dc_balance.guardband 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.max_decrease 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.max_increase 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.slope 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.vblank_target 0-u16max
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->num_crtcs
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->num_crtcs
HALF_LOCKED2 &display->drm->mode_config.mutex
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_ddi.c dp_tp_status_reg() -> tgl_dp_tp_transcoder()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state $1
RX_PATH
TASK_NOT_RUNNING