Defined in 1 files as a function:
Referenced in 1 files:
-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
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Smatch caller information:
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ctx_switch_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 28 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ctx_switch_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 44 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ctx_switch_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 45 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ctx_switch_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 79 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ctx_switch_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 28 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_dump_ip_state() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| CAPPED_DATA | 1 | instance | 1 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &hive->hive_lock | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 42 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_enable() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 42 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_get_clockgating_state() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0 |
| PARAM_VALUE | 2 | internal_offset | 27 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &m->lock | ||
| TYPE_LOCK | (struct seq_file)->lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_get_clockgating_state() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0 |
| PARAM_VALUE | 2 | internal_offset | 26 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &m->lock | ||
| TYPE_LOCK | (struct seq_file)->lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_resume_instance() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 33 |
| DATA_SOURCE | 0 | adev | $0 |
| DATA_SOURCE | 1 | instance | $1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_resume_instance() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 128 |
| DATA_SOURCE | 0 | adev | $0 |
| DATA_SOURCE | 1 | instance | $1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_resume_instance() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 128 |
| DATA_SOURCE | 0 | adev | $0 |
| DATA_SOURCE | 1 | instance | $1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_stop() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 128 |
| DATA_SOURCE | 0 | adev | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_stop() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 128 |
| DATA_SOURCE | 0 | adev | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_stop() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 138 |
| DATA_SOURCE | 0 | adev | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_gfx_stop() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 138 |
| DATA_SOURCE | 0 | adev | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &sdma_instance->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_is_idle() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-2147483646 |
| PARAM_VALUE | 2 | internal_offset | 37 |
| CAPPED_DATA | 1 | instance | 1 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_load_microcode() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 22656 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_load_microcode() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 22657 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_load_microcode() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 22656 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_mqd_init() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 1 | instance | 0 |
| PARAM_VALUE | 2 | internal_offset | 135 |
| DATA_SOURCE | 0 | adev | $0 |
| HALF_LOCKED2 | &adev->srbm_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_mqd_init() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0 |
| PARAM_VALUE | 2 | internal_offset | 138 |
| DATA_SOURCE | 0 | adev | $0 |
| HALF_LOCKED2 | &adev->srbm_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_restore_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 43 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_restore_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 43 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ring_get_wptr() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 134 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &ring->adev->cper.ring_lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ring_get_wptr() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 133 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &ring->adev->cper.ring_lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ring_set_wptr() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 133 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->gfx.gpu_clock_mutex | ||
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &adev->srbm_mutex | ||
| HALF_LOCKED2 | &kiq->ring_lock | ||
| HALF_LOCKED2 | &mux->lock | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | flags | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| HALF_LOCKED2 | ring_lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ring_set_wptr() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 134 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->gfx.gpu_clock_mutex | ||
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &adev->srbm_mutex | ||
| HALF_LOCKED2 | &kiq->ring_lock | ||
| HALF_LOCKED2 | &mux->lock | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | flags | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| HALF_LOCKED2 | ring_lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_set_trap_irq_state() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0 |
| PARAM_VALUE | 2 | internal_offset | 28 |
| DATA_SOURCE | 0 | adev | $0 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | adev->gfx.config.db_debug2 | 0-u32max |
| HOST_DATA | 0 | adev->gfx.config.mc_arb_ramcfg | 0-u32max |
| HOST_DATA | 0 | adev->gfx.num_xcc_per_xcp | 0-15[c] |
| HOST_DATA | 0 | adev->gmc.visible_vram_size | 0-4503599626321920[c] |
| HOST_DATA | 0 | adev->gmc.xgmi.node_segment_size | 0,16777216-2199006478336[c] |
| HOST_DATA | 0 | adev->hive->kobj.kref.refcount.refs.counter | s32min-s32max |
| HOST_DATA | 0 | adev->pdev->acs_capabilities | 0-u16max |
| HOST_DATA | 0 | adev->pdev->bus->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->bus->parent->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->class | 0-16777215 |
| HOST_DATA | 0 | adev->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | adev->pdev->devcap | 0-u32max |
| HOST_DATA | 0 | adev->pdev->devfn | 0-503[c] |
| HOST_DATA | 0 | adev->pdev->device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->eetlp_prefix_max | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->fm_enabled | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->hdr_type | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->ide_cfg | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->ide_tee_limit | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->irq | 0-255 |
| HOST_DATA | 0 | adev->pdev->is_cxl | 0-1 |
| HOST_DATA | 0 | adev->pdev->multifunction | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->nr_ide_mem | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->pcie_flags_reg | 0-u16max |
| HOST_DATA | 0 | adev->pdev->pcie_mpss | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->physfn->acs_capabilities | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->bus->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->bus->parent->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->class | 0-16777215 |
| HOST_DATA | 0 | adev->pdev->physfn->current_state | 0-3[c] |
| HOST_DATA | 0 | adev->pdev->physfn->devcap | 0-u32max |
| HOST_DATA | 0 | adev->pdev->physfn->devfn | 1-503[c] |
| HOST_DATA | 0 | adev->pdev->physfn->device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->eetlp_prefix_max | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->physfn->fm_enabled | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->hdr_type | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->physfn->ide_cfg | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->ide_tee_limit | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->irq | 0-255 |
| HOST_DATA | 0 | adev->pdev->physfn->is_cxl | 0-1 |
| HOST_DATA | 0 | adev->pdev->physfn->multifunction | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->nr_ide_mem | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->physfn->pcie_flags_reg | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->pcie_mpss | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->physfn->pin | 0 |
| HOST_DATA | 0 | adev->pdev->physfn->pme_support | 0-31[c] |
| HOST_DATA | 0 | adev->pdev->physfn->ptm_granularity | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->physfn->revision | 0-255 |
| HOST_DATA | 0 | adev->pdev->physfn->subsystem_device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->subsystem_vendor | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->supported_speeds | 0,2-254[c] |
| HOST_DATA | 0 | adev->pdev->physfn->transparent | 0[c] |
| HOST_DATA | 0 | adev->pdev->physfn->vendor | 0-u16max |
| HOST_DATA | 0 | adev->pdev->pin | 0 |
| HOST_DATA | 0 | adev->pdev->pme_support | 0-31[c] |
| HOST_DATA | 0 | adev->pdev->ptm_granularity | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->revision | 0-255 |
| HOST_DATA | 0 | adev->pdev->subsystem_device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->subsystem_vendor | 0-u16max |
| HOST_DATA | 0 | adev->pdev->supported_speeds | 0,2-254[c] |
| HOST_DATA | 0 | adev->pdev->transparent | 0[c] |
| HOST_DATA | 0 | adev->pdev->vendor | 0-u16max |
| HOST_DATA | 0 | adev->psp.sos.fw_version | 0-u32max |
| HOST_DATA | 0 | adev->virt.fw_reserve.checksum_key | 0-u32max |
| HOST_DATA | 0 | adev->virt.init_data_header.offset | 0-u32max |
| HOST_DATA | 0 | adev->virt.init_data_header.size_kb | 0-u32max |
| HOST_DATA | 0 | adev->vm_manager.vram_base_offset | 0-u64max[c] |
| HOST_DATA | 0 | adev->xcp_mgr->adev->discovery.debugfs_blob.size | 1-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->discovery.offset | 0-u64max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->discovery.size | 1-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->virt.fw_reserve.checksum_key | 0-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->virt.init_data_header.offset | 0-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->virt.init_data_header.size_kb | 0-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->num_xcp_per_mem_partition | 0-8[c] |
| HOST_DATA | 0 | adev->xcp_mgr->num_xcps | 1-8[c] |
| HOST_DATA | 0 | *adev->pdev->dev.driver_data | s64min-s64max |
| HOST_DATA | 0 | *adev->pdev->physfn->dev.driver_data | s64min-s64max |
| NO_OVERFLOW_SIMPLE | 0 | adev->kfd.dev->ih_wq->rescuer->task->dl.pi_se->dl_runtime | |
| NO_OVERFLOW_SIMPLE | 0 | adev->mman.num_clear_entities | |
| NO_OVERFLOW_SIMPLE | 0 | adev->nbio.ras_controller_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->nbio.ras_err_event_athub_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->psp.cmd_buf_mem->cmd.cmd_setup_tmr.buf_size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->psp.xgmi_context.context.mem_context.shared_bo->tbo.resource->size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->rmmio_size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->umc.retire_unit | |
| NO_OVERFLOW_SIMPLE | 0 | adev->virt.ack_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->virt.rcv_irq.num_types | |
| LOCK2 | irqflags | ||
| LOCK2 | 0 | &adev->irq.lock | |
| HALF_LOCKED2 | 0 | &adev->pm.mutex | |
| TYPE_LOCK | (struct amdgpu_irq)->lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_set_trap_irq_state() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 1 |
| PARAM_VALUE | 2 | internal_offset | 28 |
| DATA_SOURCE | 0 | adev | $0 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | adev->gfx.config.db_debug2 | 0-u32max |
| HOST_DATA | 0 | adev->gfx.config.mc_arb_ramcfg | 0-u32max |
| HOST_DATA | 0 | adev->gfx.num_xcc_per_xcp | 0-15[c] |
| HOST_DATA | 0 | adev->gmc.visible_vram_size | 0-4503599626321920[c] |
| HOST_DATA | 0 | adev->gmc.xgmi.node_segment_size | 0,16777216-2199006478336[c] |
| HOST_DATA | 0 | adev->hive->kobj.kref.refcount.refs.counter | s32min-s32max |
| HOST_DATA | 0 | adev->pdev->acs_capabilities | 0-u16max |
| HOST_DATA | 0 | adev->pdev->bus->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->bus->parent->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->class | 0-16777215 |
| HOST_DATA | 0 | adev->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | adev->pdev->devcap | 0-u32max |
| HOST_DATA | 0 | adev->pdev->devfn | 0-503[c] |
| HOST_DATA | 0 | adev->pdev->device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->eetlp_prefix_max | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->fm_enabled | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->hdr_type | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->ide_cfg | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->ide_tee_limit | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->irq | 0-255 |
| HOST_DATA | 0 | adev->pdev->is_cxl | 0-1 |
| HOST_DATA | 0 | adev->pdev->multifunction | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->nr_ide_mem | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->pcie_flags_reg | 0-u16max |
| HOST_DATA | 0 | adev->pdev->pcie_mpss | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->physfn->acs_capabilities | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->bus->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->bus->parent->bridge_ctl | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->class | 0-16777215 |
| HOST_DATA | 0 | adev->pdev->physfn->current_state | 0-3[c] |
| HOST_DATA | 0 | adev->pdev->physfn->devcap | 0-u32max |
| HOST_DATA | 0 | adev->pdev->physfn->devfn | 1-503[c] |
| HOST_DATA | 0 | adev->pdev->physfn->device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->eetlp_prefix_max | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->physfn->fm_enabled | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->hdr_type | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->physfn->ide_cfg | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->ide_tee_limit | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->irq | 0-255 |
| HOST_DATA | 0 | adev->pdev->physfn->is_cxl | 0-1 |
| HOST_DATA | 0 | adev->pdev->physfn->multifunction | 0-1[c] |
| HOST_DATA | 0 | adev->pdev->physfn->nr_ide_mem | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->physfn->pcie_flags_reg | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->pcie_mpss | 0-7[c] |
| HOST_DATA | 0 | adev->pdev->physfn->pin | 0 |
| HOST_DATA | 0 | adev->pdev->physfn->pme_support | 0-31[c] |
| HOST_DATA | 0 | adev->pdev->physfn->ptm_granularity | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->physfn->revision | 0-255 |
| HOST_DATA | 0 | adev->pdev->physfn->subsystem_device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->subsystem_vendor | 0-u16max |
| HOST_DATA | 0 | adev->pdev->physfn->supported_speeds | 0,2-254[c] |
| HOST_DATA | 0 | adev->pdev->physfn->transparent | 0[c] |
| HOST_DATA | 0 | adev->pdev->physfn->vendor | 0-u16max |
| HOST_DATA | 0 | adev->pdev->pin | 0 |
| HOST_DATA | 0 | adev->pdev->pme_support | 0-31[c] |
| HOST_DATA | 0 | adev->pdev->ptm_granularity | 0-255[c] |
| HOST_DATA | 0 | adev->pdev->revision | 0-255 |
| HOST_DATA | 0 | adev->pdev->subsystem_device | 0-u16max |
| HOST_DATA | 0 | adev->pdev->subsystem_vendor | 0-u16max |
| HOST_DATA | 0 | adev->pdev->supported_speeds | 0,2-254[c] |
| HOST_DATA | 0 | adev->pdev->transparent | 0[c] |
| HOST_DATA | 0 | adev->pdev->vendor | 0-u16max |
| HOST_DATA | 0 | adev->psp.sos.fw_version | 0-u32max |
| HOST_DATA | 0 | adev->virt.fw_reserve.checksum_key | 0-u32max |
| HOST_DATA | 0 | adev->virt.init_data_header.offset | 0-u32max |
| HOST_DATA | 0 | adev->virt.init_data_header.size_kb | 0-u32max |
| HOST_DATA | 0 | adev->vm_manager.vram_base_offset | 0-u64max[c] |
| HOST_DATA | 0 | adev->xcp_mgr->adev->discovery.debugfs_blob.size | 1-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->discovery.offset | 0-u64max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->discovery.size | 1-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->virt.fw_reserve.checksum_key | 0-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->virt.init_data_header.offset | 0-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->adev->virt.init_data_header.size_kb | 0-u32max |
| HOST_DATA | 0 | adev->xcp_mgr->num_xcp_per_mem_partition | 0-8[c] |
| HOST_DATA | 0 | adev->xcp_mgr->num_xcps | 1-8[c] |
| HOST_DATA | 0 | *adev->pdev->dev.driver_data | s64min-s64max |
| HOST_DATA | 0 | *adev->pdev->physfn->dev.driver_data | s64min-s64max |
| NO_OVERFLOW_SIMPLE | 0 | adev->kfd.dev->ih_wq->rescuer->task->dl.pi_se->dl_runtime | |
| NO_OVERFLOW_SIMPLE | 0 | adev->mman.num_clear_entities | |
| NO_OVERFLOW_SIMPLE | 0 | adev->nbio.ras_controller_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->nbio.ras_err_event_athub_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->psp.cmd_buf_mem->cmd.cmd_setup_tmr.buf_size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->psp.xgmi_context.context.mem_context.shared_bo->tbo.resource->size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->rmmio_size | |
| NO_OVERFLOW_SIMPLE | 0 | adev->umc.retire_unit | |
| NO_OVERFLOW_SIMPLE | 0 | adev->virt.ack_irq.num_types | |
| NO_OVERFLOW_SIMPLE | 0 | adev->virt.rcv_irq.num_types | |
| LOCK2 | irqflags | ||
| LOCK2 | 0 | &adev->irq.lock | |
| HALF_LOCKED2 | 0 | &adev->pm.mutex | |
| TYPE_LOCK | (struct amdgpu_irq)->lock |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 43 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 43 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 43 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 38 |
| CAPPED_DATA | 0 | adev->usec_timeout | 1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 42 |
| CAPPED_DATA | 0 | adev->usec_timeout | 1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 42 |
| CAPPED_DATA | 0 | adev->usec_timeout | 1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 28 |
| CAPPED_DATA | 0 | adev->usec_timeout | 1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_stop_queue() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 2 | internal_offset | 28 |
| CAPPED_DATA | 0 | adev->usec_timeout | 1 |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| LOCK2 | &sdma_instance->engine_reset_mutex | ||
| HALF_LOCKED2 | &dqm->lock_hidden | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu | ||
| TYPE_LOCK | (struct amdgpu_sdma_instance)->engine_reset_mutex |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_clock_gating() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 27 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->cg_flags | 0x800,0xffffffffffffffff |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_clock_gating() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 27 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->cg_flags | 0x800,0xffffffffffffffff |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_clock_gating() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 27 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_clock_gating() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 27 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_light_sleep() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 26 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->cg_flags | 0x400,0xffffffffffffffff |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_light_sleep() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 26 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->cg_flags | 0x400,0xffffffffffffffff |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_light_sleep() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 26 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_update_medium_grain_light_sleep() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0-s32max |
| PARAM_VALUE | 2 | internal_offset | 26 |
| CAPPED_DATA | 0 | adev->sdma.num_instances | 1 |
| CAPPED_DATA | 1 | instance | 1 |
| DATA_SOURCE | 0 | adev | $0 |
| PARAM_COMPARE | 0 | adev->sdma.num_instances | > $1 |
| PARAM_COMPARE | 1 | instance | < $0->sdma.num_instances |
| BIT_INFO | 0 | adev->virt.caps | 0x0,0xfffffffb |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 1 | instance | unit_array_size |
| HALF_LOCKED2 | &adev->reset_domain->sem | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &drm_unplug_srcu |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_wait_for_idle() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 0 |
| PARAM_VALUE | 2 | internal_offset | 37 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &adev->grbm_idx_mutex | ||
| HALF_LOCKED2 | &adev->reset_domain->sem |
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_wait_for_idle() -> sdma_v5_0_get_reg_offset()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | adev | 4096-ptr_max |
| PARAM_VALUE | 1 | instance | 1 |
| PARAM_VALUE | 2 | internal_offset | 37 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &adev->grbm_idx_mutex | ||
| HALF_LOCKED2 | &adev->reset_domain->sem |