| PARAM_VALUE |
0 |
rtwdev |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip->bss_clr_vld.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->bss_clr_vld.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->c2h_counter_reg.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->c2h_counter_reg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->chip_gen |
0 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_p20_pagcugc_en.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_p20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_s20_pagcugc_en.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_s20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_p20_pagcugc_en.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_p20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_s20_pagcugc_en.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_s20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->h2c_counter_reg.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->h2c_counter_reg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->agg_limit.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->agg_limit.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->bfee_ctrl.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->bfee_ctrl.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->muedca_ctrl.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->muedca_ctrl.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->narrow_bw_ru_dis.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->narrow_bw_ru_dis.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->ra_agg_limit.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->ra_agg_limit.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->txcnt_limit.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->txcnt_limit.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->wow_ctrl.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->wow_ctrl.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->ops |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip->ops->disable_bb_rf |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->ampdu_miss.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->ampdu_miss.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->brk.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->brk.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->brk_option.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->brk_option.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cca_spoofing.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cca_spoofing.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_brk.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_brk.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_cca.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_cca.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_sfd_gg.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_sfd_gg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_sig_gg.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_sig_gg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_spoofing.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_spoofing.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_txen.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_txen.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_txon.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_txon.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->enable_all_cnt.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->enable_all_cnt.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->lsig_brk_l_th.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->lsig_brk_l_th.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->lsig_brk_s_th.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->lsig_brk_s_th.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->ofdm_cca.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->ofdm_cca.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->r1b_rr_sel.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->r1b_rr_sel.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->r1b_rx_rpt_rst.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->r1b_rx_rpt_rst.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rst_all_cnt.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rst_all_cnt.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rxl_err_parity.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rxl_err_parity.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rxl_err_rate.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rxl_err_rate.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->search_fail.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->search_fail.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_get.addr |
0,96,501,512,1344,1436,1440,1448,1452,1840,3080,3084,3088,3092 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_get.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->priv->continual_io_error.counter |
s32min-s32max |
| DATA_SOURCE |
0 |
rtwdev |
$0 |