Defined in 8 files as a macro:
- drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c, line 95 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_3_1_offset.h, line 1174 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h, line 63 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h, line 69 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h, line 8225 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h, line 4055 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h, line 3395 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h, line 63 (as a macro)