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Defined in 1 files as a function:

Referenced in 6 files:

Smatch caller information:

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c dpu_hw_setup_format_impl() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
PARAM_VALUE 0 cfg->ubwc_enc_version 805306368-1073741823
FUZZY_MAX 0 cfg->ubwc_enc_version 805306368
HARD_MAX 0 cfg->ubwc_enc_version 1073741823
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 irq

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c dpu_hw_setup_format_impl() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
PARAM_VALUE 0 cfg->ubwc_enc_version 536870912-805306367
FUZZY_MAX 0 cfg->ubwc_enc_version 536870912
HARD_MAX 0 cfg->ubwc_enc_version 805306367
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 irq

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c dpu_hw_setup_format_impl() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
PARAM_VALUE 0 cfg->ubwc_enc_version 268435456-536870911
FUZZY_MAX 0 cfg->ubwc_enc_version 268435456
HARD_MAX 0 cfg->ubwc_enc_version 536870911
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 irq

drivers/gpu/drm/msm/adreno/adreno_gpu.c adreno_get_param() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 1-u64max
RX_PATH

drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c iris_hfi_gen2_packet_sys_init() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
RX_PATH
TASK_NOT_RUNNING
LOCK2 &core->lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct iris_core)->lock

drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c iris_hfi_gen2_packet_sys_init() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
RX_PATH
TASK_NOT_RUNNING
LOCK2 &core->lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct iris_core)->lock

drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c iris_hfi_gen2_packet_sys_init() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
RX_PATH
TASK_NOT_RUNNING
LOCK2 &core->lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct iris_core)->lock

drivers/gpu/drm/msm/adreno/a8xx_gpu.c a8xx_set_ubwc_config() -> qcom_ubwc_swizzle()

Type Parameter Key Value
RX_PATH
TASK_NOT_RUNNING
LOCK2 &a6xx_gpu->gmu.lock
HALF_LOCKED2 &gpu->lock
HALF_LOCKED2 &init_lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 _T->lock
TYPE_LOCK (struct a6xx_gmu)->lock

drivers/gpu/drm/msm/adreno/a8xx_gpu.c a8xx_set_ubwc_config() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
RX_PATH
TASK_NOT_RUNNING
LOCK2 &a6xx_gpu->gmu.lock
HALF_LOCKED2 &gpu->lock
HALF_LOCKED2 &init_lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 _T->lock
TYPE_LOCK (struct a6xx_gmu)->lock

drivers/gpu/drm/msm/adreno/a6xx_gpu.c a6xx_set_ubwc_config() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 4096-ptr_max
RX_PATH
TASK_NOT_RUNNING
LOCK2 &a6xx_gpu->gmu.lock
HALF_LOCKED2 &gpu->lock
HALF_LOCKED2 &init_lock
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 _T->lock
TYPE_LOCK (struct a6xx_gmu)->lock

drivers/gpu/drm/msm/msm_mdss.c msm_mdss_4x_setup_ubwc() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 1-u64max
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/msm/msm_mdss.c msm_mdss_5x_setup_ubwc() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 1-u64max
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/msm/msm_mdss.c msm_mdss_6x_setup_ubwc() -> qcom_ubwc_swizzle()

Type Parameter Key Value
PARAM_VALUE 0 cfg 1-u64max
RX_PATH
TASK_NOT_RUNNING