Defined in 1 files as a function:
Referenced in 1 files:
-
drivers/crypto/intel/qat/qat_common/qat_hal.c
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Smatch caller information:
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_check_ae_active() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 1 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->alloc_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->alloc_mutex.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_io_tlb_pools.next | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_io_tlb_pools.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_io_tlb_pools.next->prev->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_uses_io_tlb | 1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->attach_deferred | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 0 | handle->sobj_handle | 4096-ptr_max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 24 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 0 | handle->pci_dev | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_check_ae_active() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 1 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->alloc_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->alloc_mutex.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_io_tlb_pools.next | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_io_tlb_pools.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_io_tlb_pools.next->prev->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.dma_uses_io_tlb | 1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->attach_deferred | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 0 | handle->sobj_handle | 4096-ptr_max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 68 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 0 | handle->pci_dev | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_check_ae_alive() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 324 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | r find_next_bit |
| PARAM_COMPARE | 1 | ae | < $0->hal_handle->ae_max_num |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_check_ae_alive() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 324 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | r find_next_bit |
| PARAM_COMPARE | 1 | ae | < $0->hal_handle->ae_max_num |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_chip_init() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->cfg_ae_mask | u32max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fcu_ctl_csr | 0,2240,4096 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_hi | 0,2256,4120 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_lo | 0,2252,4116 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_csr | 0,2244,4112 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_pos | 0,22 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_sts_csr | 0,2244,4100 |
| PARAM_VALUE | 0 | handle->chip_info->glb_clk_enable_csr | 2404,2640 |
| PARAM_VALUE | 0 | handle->chip_info->icp_rst_csr | 2360,2572 |
| PARAM_VALUE | 0 | handle->chip_info->lm_size | 1024,1280 |
| PARAM_VALUE | 0 | handle->chip_info->misc_ctl_csr | 2564,2720 |
| PARAM_VALUE | 0 | handle->chip_info->mmp_sram_size | 0,262144 |
| PARAM_VALUE | 0 | handle->chip_info->wakeup_event_val | 65536,2147483648 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_local_csr_addr_v | 6144-18446744073709549568 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_xfer_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_cap_g_ctl_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_ep_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 16384 |
| PARAM_VALUE | 0 | handle->hal_handle->revision_id | 0-255 |
| PARAM_VALUE | 0 | handle->hal_handle->slice_mask | 0-u16max |
| PARAM_VALUE | 0 | handle->hal_handle->upc_mask | 131071 |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->device | 1077,6626,14280,18752,18754,18756,18758,18760 |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 336 |
| BUF_SIZE | 0 | handle | 96 |
| BUF_SIZE | 0 | handle->chip_info | 60 |
| BUF_SIZE | 0 | handle->hal_handle | 368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | r find_next_bit |
| FUZZY_MAX | 0 | handle->chip_info->fcu_ctl_csr | 4096 |
| FUZZY_MAX | 0 | handle->chip_info->fcu_dram_addr_hi | 4120 |
| FUZZY_MAX | 0 | handle->chip_info->fcu_dram_addr_lo | 4116 |
| FUZZY_MAX | 0 | handle->chip_info->fcu_loaded_ae_csr | 4112 |
| FUZZY_MAX | 0 | handle->chip_info->fcu_loaded_ae_pos | 22 |
| FUZZY_MAX | 0 | handle->chip_info->fcu_sts_csr | 4100 |
| FUZZY_MAX | 0 | handle->chip_info->glb_clk_enable_csr | 2640 |
| FUZZY_MAX | 0 | handle->chip_info->icp_rst_csr | 2572 |
| FUZZY_MAX | 0 | handle->chip_info->lm_size | 1280 |
| FUZZY_MAX | 0 | handle->chip_info->misc_ctl_csr | 2720 |
| FUZZY_MAX | 0 | handle->chip_info->mmp_sram_size | 262144 |
| FUZZY_MAX | 0 | handle->chip_info->wakeup_event_val | 2147483648 |
| FUZZY_MAX | 0 | handle->pci_dev->device | 18758 |
| PARAM_COMPARE | 1 | ae | < $0->hal_handle->ae_max_num |
| BIT_INFO | 0 | handle->chip_info->fcu_ctl_csr | 0x0,0x18c0 |
| BIT_INFO | 0 | handle->chip_info->fcu_dram_addr_hi | 0x0,0x18d8 |
| BIT_INFO | 0 | handle->chip_info->fcu_dram_addr_lo | 0x0,0x18dc |
| BIT_INFO | 0 | handle->chip_info->fcu_loaded_ae_csr | 0x0,0x18d4 |
| BIT_INFO | 0 | handle->chip_info->fcu_loaded_ae_pos | 0x0,0x16 |
| BIT_INFO | 0 | handle->chip_info->fcu_sts_csr | 0x0,0x18c4 |
| BIT_INFO | 0 | handle->chip_info->glb_clk_enable_csr | 0x840,0xffffffffffffffff |
| BIT_INFO | 0 | handle->chip_info->icp_rst_csr | 0x808,0xffffffffffffffff |
| BIT_INFO | 0 | handle->chip_info->lm_size | 0x400,0xffffffffffffffff |
| BIT_INFO | 0 | handle->chip_info->misc_ctl_csr | 0xa00,0xffffffffffffffff |
| BIT_INFO | 0 | handle->chip_info->mmp_sram_size | 0x0,0x40000 |
| BIT_INFO | 0 | handle->chip_info->wakeup_event_val | 0x0,0x80010000 |
| HARD_MAX | 0 | handle->chip_info->fcu_ctl_csr | 4096 |
| HARD_MAX | 0 | handle->chip_info->fcu_dram_addr_hi | 4120 |
| HARD_MAX | 0 | handle->chip_info->fcu_dram_addr_lo | 4116 |
| HARD_MAX | 0 | handle->chip_info->fcu_loaded_ae_csr | 4112 |
| HARD_MAX | 0 | handle->chip_info->fcu_loaded_ae_pos | 22 |
| HARD_MAX | 0 | handle->chip_info->fcu_sts_csr | 4100 |
| HARD_MAX | 0 | handle->chip_info->glb_clk_enable_csr | 2640 |
| HARD_MAX | 0 | handle->chip_info->icp_rst_csr | 2572 |
| HARD_MAX | 0 | handle->chip_info->lm_size | 1280 |
| HARD_MAX | 0 | handle->chip_info->misc_ctl_csr | 2720 |
| HARD_MAX | 0 | handle->chip_info->mmp_sram_size | 262144 |
| HARD_MAX | 0 | handle->chip_info->wakeup_event_val | 2147483648 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_clear_gpr() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->cfg_ae_mask | u32max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->dual_sign | 1 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_ctl_csr | 0,2240,4096 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_hi | 0,2256,4120 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_lo | 0,2252,4116 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_csr | 0,2244,4112 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_pos | 0,22 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_sts_csr | 0,2244,4100 |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->chip_info->glb_clk_enable_csr | 2404,2640 |
| PARAM_VALUE | 0 | handle->chip_info->icp_rst_csr | 2360,2572 |
| PARAM_VALUE | 0 | handle->chip_info->lm_size | 1024,1280 |
| PARAM_VALUE | 0 | handle->chip_info->misc_ctl_csr | 2564,2720 |
| PARAM_VALUE | 0 | handle->chip_info->mmp_sram_size | 0,262144 |
| PARAM_VALUE | 0 | handle->chip_info->reset_delay_us | 3 |
| PARAM_VALUE | 0 | handle->chip_info->wakeup_event_val | 65536,2147483648 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_local_csr_addr_v | 6144-18446744073709549568 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_xfer_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_cap_g_ctl_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_ep_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 16384 |
| PARAM_VALUE | 0 | handle->hal_handle->revision_id | 0-255 |
| PARAM_VALUE | 0 | handle->hal_handle->slice_mask | 0-u16max |
| PARAM_VALUE | 0 | handle->hal_handle->upc_mask | 131071 |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 352 |
| BUF_SIZE | 0 | handle | 96 |
| BUF_SIZE | 0 | handle->chip_info | 60 |
| BUF_SIZE | 0 | handle->hal_handle | 368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | r find_next_bit |
| PARAM_COMPARE | 1 | ae | < $0->hal_handle->ae_max_num |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_clear_gpr() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->cfg_ae_mask | u32max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->dual_sign | 1 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_ctl_csr | 0,2240,4096 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_hi | 0,2256,4120 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_lo | 0,2252,4116 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_csr | 0,2244,4112 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_pos | 0,22 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_sts_csr | 0,2244,4100 |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->chip_info->glb_clk_enable_csr | 2404,2640 |
| PARAM_VALUE | 0 | handle->chip_info->icp_rst_csr | 2360,2572 |
| PARAM_VALUE | 0 | handle->chip_info->lm_size | 1024,1280 |
| PARAM_VALUE | 0 | handle->chip_info->misc_ctl_csr | 2564,2720 |
| PARAM_VALUE | 0 | handle->chip_info->mmp_sram_size | 0,262144 |
| PARAM_VALUE | 0 | handle->chip_info->reset_delay_us | 3 |
| PARAM_VALUE | 0 | handle->chip_info->wakeup_event_val | 65536,2147483648 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_local_csr_addr_v | 6144-18446744073709549568 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_xfer_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_cap_g_ctl_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_ep_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 16384 |
| PARAM_VALUE | 0 | handle->hal_handle->revision_id | 0-255 |
| PARAM_VALUE | 0 | handle->hal_handle->slice_mask | 0-u16max |
| PARAM_VALUE | 0 | handle->hal_handle->upc_mask | 131071 |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle | 96 |
| BUF_SIZE | 0 | handle->chip_info | 60 |
| BUF_SIZE | 0 | handle->hal_handle | 368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | r find_next_bit |
| PARAM_COMPARE | 1 | ae | < $0->hal_handle->ae_max_num |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_clear_gpr() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->cfg_ae_mask | u32max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->dual_sign | 1 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_ctl_csr | 0,2240,4096 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_hi | 0,2256,4120 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_dram_addr_lo | 0,2252,4116 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_csr | 0,2244,4112 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_loaded_ae_pos | 0,22 |
| PARAM_VALUE | 0 | handle->chip_info->fcu_sts_csr | 0,2244,4100 |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->chip_info->glb_clk_enable_csr | 2404,2640 |
| PARAM_VALUE | 0 | handle->chip_info->icp_rst_csr | 2360,2572 |
| PARAM_VALUE | 0 | handle->chip_info->lm_size | 1024,1280 |
| PARAM_VALUE | 0 | handle->chip_info->misc_ctl_csr | 2564,2720 |
| PARAM_VALUE | 0 | handle->chip_info->mmp_sram_size | 0,262144 |
| PARAM_VALUE | 0 | handle->chip_info->reset_delay_us | 3 |
| PARAM_VALUE | 0 | handle->chip_info->wakeup_event_val | 65536,2147483648 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_local_csr_addr_v | 6144-18446744073709549568 |
| PARAM_VALUE | 0 | handle->hal_cap_ae_xfer_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_cap_g_ctl_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_ep_csr_addr_v | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 16384 |
| PARAM_VALUE | 0 | handle->hal_handle->revision_id | 0-255 |
| PARAM_VALUE | 0 | handle->hal_handle->slice_mask | 0-u16max |
| PARAM_VALUE | 0 | handle->hal_handle->upc_mask | 131071 |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 68 |
| BUF_SIZE | 0 | handle | 96 |
| BUF_SIZE | 0 | handle->chip_info | 60 |
| BUF_SIZE | 0 | handle->hal_handle | 368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | r find_next_bit |
| PARAM_COMPARE | 1 | ae | < $0->hal_handle->ae_max_num |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_disable_ctx() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_enable_ctx() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 24 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 28 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 68 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 20 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 76 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 352 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_get_uwords() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 352 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_get_uwords() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 0 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_get_uwords() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 4 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_get_uwords() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 8 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_get_wakeup_event() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 32 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_get_wakeup_event() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 80 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_put_rel_nn() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->chip_info->nn | 1 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 24 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_put_rel_rd_xfer() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 1 | ae | 0-16 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_put_rel_wr_xfer() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 24 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_put_sig_event() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-64 |
| PARAM_VALUE | 1 | ae | 0-63 |
| PARAM_VALUE | 2 | csr | 32 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_put_wakeup_event() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 32 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_indr_csr() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 32 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_indr_csr() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 64,72,96,104,120,204,212,224,232,248,252,268,276 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| DATA_SOURCE | 2 | csr | $3 |
| HARD_MAX | 2 | csr | 276 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_rel_reg() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 68 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_rel_reg() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 20 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_rel_reg() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 24 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_rel_reg() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 0 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_rd_rel_reg() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 2 | csr | 16 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_set_ae_ctx_mode() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-64,2147483648-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->obj_handle->uimage_num | 1-s32max |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->attach_deferred | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->device | 0-18760 |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle->obj_handle | 27728 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 0 | handle->obj_handle->uimage_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_set_ae_lm_mode() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-64,2147483648-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->obj_handle->uimage_num | 1-s32max |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->attach_deferred | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->device | 0-18760 |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle->obj_handle | 27728 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 0 | handle->obj_handle->uimage_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_set_ae_nn_mode() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->chip_info->nn | 1 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-64,2147483648-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->obj_handle->uimage_num | 1-s32max |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->attach_deferred | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->device | 0-18760 |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle->obj_handle | 27728 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 0 | handle->obj_handle->uimage_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_set_ae_tindex_mode() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->chip_info->lm2lm3 | 1 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-64,2147483648-u32max |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->obj_handle->uimage_num | 1-s32max |
| PARAM_VALUE | 0 | handle->pci_dev | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->attach_deferred | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->device | 0-18760 |
| PARAM_VALUE | 1 | ae | 0-64 |
| PARAM_VALUE | 2 | csr | 24 |
| BUF_SIZE | 0 | handle->obj_handle | 27728 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| CAPPED_DATA | 0 | handle->obj_handle->uimage_num | 1 |
| CAPPED_DATA | 1 | ae | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_wait_cycles() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 324 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_wait_cycles() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->hal_handle->max_ustore | 2-u32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 68 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_wait_cycles() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 324 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_wr_indr_csr() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 32 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_wr_umem() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-17 |
| PARAM_VALUE | 0 | handle->obj_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu->pci_32bit_workaround | 0-1 |
| PARAM_VALUE | 0 | handle->pci_dev->dev.iommu_group->default_domain | 0-s64max |
| PARAM_VALUE | 2 | csr | 0 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |
drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_wr_uwords() -> qat_hal_rd_ae_csr()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->chip_info->fw_auth | 0 |
| PARAM_VALUE | 0 | handle->hal_handle | 4096-ptr_max |
| PARAM_VALUE | 0 | handle->hal_handle->ae_max_num | 1-u32max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->available_count | 0-s64max |
| PARAM_VALUE | 0 | handle->pci_dev->dev.cma_area->nranges | s32min-s32max |
| PARAM_VALUE | 2 | csr | 0 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle | (-1),96 |
| BUF_SIZE | 0 | handle->chip_info | (-1),60 |
| BUF_SIZE | 0 | handle->hal_handle | (-1),368 |
| CAPPED_DATA | 0 | handle->hal_handle->ae_max_num | 1 |
| DATA_SOURCE | 0 | handle | $0 |
| DATA_SOURCE | 1 | ae | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| LOCK2 | &accel_dev->state_lock | ||
| HALF_LOCKED2 | &of->mutex | ||
| HALF_LOCKED2 | &pdev->dev.mutex | ||
| HALF_LOCKED2 | global &pci_rescan_remove_lock | ||
| TYPE_LOCK | (struct adf_accel_dev)->state_lock |