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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_clear_gpr() -> qat_hal_disable_ctx()

Type Parameter Key Value
PARAM_VALUE 0 handle 4096-ptr_max
PARAM_VALUE 0 handle->cfg_ae_mask u32max
PARAM_VALUE 0 handle->chip_info 4096-ptr_max
PARAM_VALUE 0 handle->chip_info->dual_sign 1
PARAM_VALUE 0 handle->chip_info->fcu_ctl_csr 0,2240,4096
PARAM_VALUE 0 handle->chip_info->fcu_dram_addr_hi 0,2256,4120
PARAM_VALUE 0 handle->chip_info->fcu_dram_addr_lo 0,2252,4116
PARAM_VALUE 0 handle->chip_info->fcu_loaded_ae_csr 0,2244,4112
PARAM_VALUE 0 handle->chip_info->fcu_loaded_ae_pos 0,22
PARAM_VALUE 0 handle->chip_info->fcu_sts_csr 0,2244,4100
PARAM_VALUE 0 handle->chip_info->fw_auth 0
PARAM_VALUE 0 handle->chip_info->glb_clk_enable_csr 2404,2640
PARAM_VALUE 0 handle->chip_info->icp_rst_csr 2360,2572
PARAM_VALUE 0 handle->chip_info->lm_size 1024,1280
PARAM_VALUE 0 handle->chip_info->misc_ctl_csr 2564,2720
PARAM_VALUE 0 handle->chip_info->mmp_sram_size 0,262144
PARAM_VALUE 0 handle->chip_info->reset_delay_us 3
PARAM_VALUE 0 handle->chip_info->wakeup_event_val 65536,2147483648
PARAM_VALUE 0 handle->hal_cap_ae_local_csr_addr_v 6144-18446744073709549568
PARAM_VALUE 0 handle->hal_cap_ae_xfer_csr_addr_v 4096-ptr_max
PARAM_VALUE 0 handle->hal_cap_g_ctl_csr_addr_v 4096-ptr_max
PARAM_VALUE 0 handle->hal_ep_csr_addr_v 4096-ptr_max
PARAM_VALUE 0 handle->hal_handle 4096-ptr_max
PARAM_VALUE 0 handle->hal_handle->ae_max_num 1-17
PARAM_VALUE 0 handle->hal_handle->max_ustore 16384
PARAM_VALUE 0 handle->hal_handle->revision_id 0-255
PARAM_VALUE 0 handle->hal_handle->slice_mask 0-u16max
PARAM_VALUE 0 handle->hal_handle->upc_mask 131071
PARAM_VALUE 0 handle->pci_dev 4096-ptr_max
PARAM_VALUE 1 ae 0-16
PARAM_VALUE 2 ctx_mask 255
BUF_SIZE 0 handle 96
BUF_SIZE 0 handle->chip_info 60
BUF_SIZE 0 handle->hal_handle 368
CAPPED_DATA 0 handle->hal_handle->ae_max_num 1
CAPPED_DATA 1 ae 1
DATA_SOURCE 0 handle $0
DATA_SOURCE 1 ae r find_next_bit
PARAM_COMPARE 1 ae < $0->hal_handle->ae_max_num
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &accel_dev->state_lock
HALF_LOCKED2 &of->mutex
HALF_LOCKED2 &pdev->dev.mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 global &pci_rescan_remove_lock
TYPE_LOCK (struct adf_accel_dev)->state_lock

drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_exec_micro_inst() -> qat_hal_disable_ctx()

Type Parameter Key Value
PARAM_VALUE 0 handle 4096-ptr_max
PARAM_VALUE 0 handle->chip_info 4096-ptr_max
PARAM_VALUE 0 handle->chip_info->fw_auth 0
PARAM_VALUE 0 handle->hal_handle 4096-ptr_max
PARAM_VALUE 0 handle->hal_handle->ae_max_num 1-u32max
PARAM_VALUE 0 handle->hal_handle->max_ustore 2-u32max
PARAM_VALUE 0 handle->obj_handle 4096-ptr_max
PARAM_VALUE 0 handle->pci_dev->dev.cma_area->available_count 0-s64max
PARAM_VALUE 0 handle->pci_dev->dev.cma_area->nranges s32min-s32max
PARAM_VALUE 0 handle->pci_dev->dev.iommu->pci_32bit_workaround 0-1
CAPPED_DATA 0 handle->hal_handle->ae_max_num 1
DATA_SOURCE 0 handle $0
DATA_SOURCE 1 ae $1
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &accel_dev->state_lock
HALF_LOCKED2 &of->mutex
HALF_LOCKED2 &pdev->dev.mutex
HALF_LOCKED2 global &pci_rescan_remove_lock
TYPE_LOCK (struct adf_accel_dev)->state_lock

drivers/crypto/intel/qat/qat_common/qat_hal.c qat_hal_stop() -> qat_hal_disable_ctx()

Type Parameter Key Value
PARAM_VALUE 0 handle 4096-ptr_max
PARAM_VALUE 0 handle->chip_info 4096-ptr_max
PARAM_VALUE 0 handle->chip_info->fw_auth 0
PARAM_VALUE 1 ae 0-254
PARAM_VALUE 2 ctx_mask 255
CAPPED_DATA 1 ae 1
DATA_SOURCE 0 handle $0
DATA_SOURCE 1 ae $1
DATA_SOURCE 2 ctx_mask $2
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &accel_dev->state_lock
HALF_LOCKED2 &dev->mutex
HALF_LOCKED2 &of->mutex
HALF_LOCKED2 &pdev->dev.mutex
HALF_LOCKED2 &pool->lock
HALF_LOCKED2 global &pci_rescan_remove_lock
TYPE_LOCK (struct adf_accel_dev)->state_lock