Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/gma500/gtt.c psb_gtt_fini() -> psb_gtt_disable()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dev_priv | 4096-ptr_max |
| PARAM_VALUE | 0 | dev_priv->gtt_map | 0 |
| DATA_SOURCE | 0 | dev_priv | r to_drm_psb_private |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/gma500/gtt.c psb_gtt_init() -> psb_gtt_disable()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dev_priv | 4096-ptr_max |
| PARAM_VALUE | 0 | dev_priv->gmch_ctrl | 0 |
| PARAM_VALUE | 0 | dev_priv->gtt.mmu_gatt_start | 3758096384 |
| PARAM_VALUE | 0 | dev_priv->gtt_map | 0 |
| PARAM_VALUE | 0 | dev_priv->gtt_mem | 4096-ptr_max |
| PARAM_VALUE | 0 | dev_priv->gtt_mutex.dep_map->name | 0-255 |
| PARAM_VALUE | 0 | dev_priv->gtt_mutex.first_waiter | 0 |
| PARAM_VALUE | 0 | dev_priv->gtt_mutex.magic | 4096-ptr_max |
| PARAM_VALUE | 0 | dev_priv->gtt_mutex.osq.tail.counter | 0 |
| PARAM_VALUE | 0 | dev_priv->gtt_mutex.owner.counter | 0 |
| PARAM_VALUE | 0 | dev_priv->vdc_reg | 4096-ptr_max |
| DATA_SOURCE | 0 | dev_priv | r to_drm_psb_private |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | dev_priv->apm_base | 0-u16max |
| HOST_DATA | 0 | dev_priv->apm_reg | 0-u32max |
| HOST_DATA | 0 | dev_priv->backlight_duty_cycle | s32min-s32max |
| HOST_DATA | 0 | dev_priv->backlight_enabled | 0-1 |
| HOST_DATA | 0 | dev_priv->backlight_level | s32min-s32max |
| HOST_DATA | 0 | dev_priv->blc_adj1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->blc_adj2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->bpp | 0-u32max |
| HOST_DATA | 0 | dev_priv->bpp2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->child_dev_num | s32min-s32max |
| HOST_DATA | 0 | dev_priv->core_freq | 0-u32max |
| HOST_DATA | 0 | dev_priv->crt_ddc_pin | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.clientlist_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.clientlist_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.driver_features | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.filelist_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.filelist_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.gem_lru_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.gem_lru_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.if_version | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.master_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.master_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.max_vblank_count | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.async_page_flip | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.blob_lock.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.blob_lock.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connection_mutex.mutex.base.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connection_mutex.mutex.base.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connector_free_work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connector_ida.xa.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.cursor_height | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.cursor_width | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.delayed_event | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.fb_lock.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.fb_lock.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.fb_modifiers_not_supported | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.idr_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.idr_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.max_height | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.max_width | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.min_height | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.min_width | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.normalize_zpos | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_colorop | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_connector | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_crtc | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_encoder | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_fb | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_total_plane | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.object_idr.idr_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.object_idr.idr_next | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.object_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.cpu | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.timer.expires | 0-u64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.timer.flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.magic | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.owner_cpu | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.locked | 0-255 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.locked_pending | 0-u16max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.pending | 0-255 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.tail | 0-u16max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.val.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.poll_enabled | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.poll_running | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.prefer_shadow | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.preferred_depth | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.quirk_addfb_prefer_host_byte_order | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.quirk_addfb_prefer_xbgr_30bpp | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.tile_idr.idr_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.tile_idr.idr_next | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.tile_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.num_crtcs | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_idr.idr_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_idr.idr_next | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_lock.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_lock.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.open_count.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.ref.refcount.refs.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.registered | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.switch_power_state | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.unplugged | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.vblank_disable_immediate | 0-1 |
| HOST_DATA | 0 | dev_priv->dplla_96mhz | 0-1 |
| HOST_DATA | 0 | dev_priv->dsr_enable | 0-1 |
| HOST_DATA | 0 | dev_priv->dsr_fb_update | 0-u32max |
| HOST_DATA | 0 | dev_priv->edp.bpp | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.initialized | 0-1 |
| HOST_DATA | 0 | dev_priv->edp.lanes | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.pps.t10 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t11_t12 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t1_t3 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t8 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t9 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.preemphasis | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.rate | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.support | 0-1 |
| HOST_DATA | 0 | dev_priv->edp.vswing | s32min-s32max |
| HOST_DATA | 0 | dev_priv->fuse_reg_value | 0-u32max |
| HOST_DATA | 0 | dev_priv->gatt_free_offset | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hactive_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hactive_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hblank_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hblank_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hborder | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.height_mm_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.height_mm_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_offset_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_offset_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_positive | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_pulse_width_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_pulse_width_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.interlaced | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.pixel_clock | 0-u16max |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.separate_sync | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.stereo | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.unknown0 | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.unknown6 | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vactive_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vactive_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vblank_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vblank_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vborder | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_offset_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_offset_lo | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_positive | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_pulse_width_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_pulse_width_lo | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.width_mm_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.width_mm_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.PP_Cycle_Delay | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.PP_Off_Sequencing | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.PP_On_Sequencing | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.Panel_Backlight_Inverter_Descriptor | 0-u16max |
| HOST_DATA | 0 | dev_priv->gct_data.Panel_MIPI_Display_Descriptor | 0-u16max |
| HOST_DATA | 0 | dev_priv->gct_data.Panel_Port_Control | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.bpi | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.pt | 0-255 |
| HOST_DATA | 0 | dev_priv->gmch_ctrl | 0 |
| HOST_DATA | 0 | dev_priv->gtt.gtt_phys_start | 0,4096-4294963200 |
| HOST_DATA | 0 | dev_priv->gtt.gtt_start | 0-u32max |
| HOST_DATA | 0 | dev_priv->gtt.stolen_size | 0-u64max |
| HOST_DATA | 0 | dev_priv->gtt.vram_stolen_size | 0-u64max |
| HOST_DATA | 0 | dev_priv->gtt_mutex.osq.tail.counter | 0 |
| HOST_DATA | 0 | dev_priv->gtt_mutex.owner.counter | 0 |
| HOST_DATA | 0 | dev_priv->has_gct | 0-1 |
| HOST_DATA | 0 | dev_priv->hotplug_supported_mask | 0-u32max |
| HOST_DATA | 0 | dev_priv->hotplug_work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->iLVDS_enable | 0-u32max |
| HOST_DATA | 0 | dev_priv->int_crt_support | 0-1 |
| HOST_DATA | 0 | dev_priv->int_tv_support | 0-1 |
| HOST_DATA | 0 | dev_priv->irq_enabled | 0-1 |
| HOST_DATA | 0 | dev_priv->is_lvds_on | 0-1 |
| HOST_DATA | 0 | dev_priv->is_mipi_on | 0-1 |
| HOST_DATA | 0 | dev_priv->lpc_gpio_base | 0-u16max |
| HOST_DATA | 0 | dev_priv->lvds_dither | 0-1 |
| HOST_DATA | 0 | dev_priv->lvds_enabled_in_vbt | 0-1 |
| HOST_DATA | 0 | dev_priv->lvds_ssc_freq | s32min-s32max |
| HOST_DATA | 0 | dev_priv->lvds_use_ssc | 0-1 |
| HOST_DATA | 0 | dev_priv->lvds_vbt | 0-1 |
| HOST_DATA | 0 | dev_priv->mipi_ctrl_display | 0-u32max |
| HOST_DATA | 0 | dev_priv->mmap_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->mmap_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->mode_dev.backlight_duty_cycle | s32min-s32max |
| HOST_DATA | 0 | dev_priv->mode_dev.panel_wants_dither | 0-1 |
| HOST_DATA | 0 | dev_priv->mode_dev.saveBLC_PWM_CTL | 0-u32max |
| HOST_DATA | 0 | dev_priv->modeset | 0-1 |
| HOST_DATA | 0 | dev_priv->num_pipe | 0-u32max |
| HOST_DATA | 0 | dev_priv->opregion.asle_work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->ospm_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->panel_type | 0-255 |
| HOST_DATA | 0 | dev_priv->panel_wants_dither | 0-1 |
| HOST_DATA | 0 | dev_priv->pge_ctl | 0-u32max |
| HOST_DATA | 0 | dev_priv->platform_rev_id | 0-255 |
| HOST_DATA | 0 | dev_priv->pm_initialized | 0-1 |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveADPA | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveDSPARB | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveDSPCLK_GATE_D | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveIER | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveIMR | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveLBB | 0-255 |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveLVDS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePFIT_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePFIT_PGM_RATIOS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_CYCLE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_OFF_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_ON_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveRAMCLK_GATE_D | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveVGACNTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveADPA | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveBCLRPAT_A | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveBCLRPAT_B | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveCHICKENBIT | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveCLOCKGATING | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPACURSOR_BASE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPACURSOR_CTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPACURSOR_POS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPARB | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPBCURSOR_BASE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPBCURSOR_CTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPBCURSOR_POS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW3 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW4 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW5 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW6 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDVOA | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDVOB | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDVOC | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveHISTOGRAM_INT_CONTROL_REG | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveHISTOGRAM_LOGIC_CONTROL_REG | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveLVDS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC0 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC3 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC4 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC5 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OVADD | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC0 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC3 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC4 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC5 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OVADD | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePERF_MODE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePFIT_AUTO_RATIOS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePFIT_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePFIT_PGM_RATIOS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_CYCLE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_DIVISOR | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_OFF | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_OFF_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_ON | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_ON_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePWM_CONTROL_LOGIC | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVCLK_DIVISOR_VGA0 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVCLK_DIVISOR_VGA1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVCLK_POST_DIV | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVGACNTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveBLC_PWM_CTL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveBLC_PWM_CTL2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveBSM | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveVBT | 0-u32max |
| HOST_DATA | 0 | dev_priv->stolen_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->use_msi | 0-1 |
| HOST_DATA | 0 | dev_priv->vdc_irq_mask | 0-u32max |
| HOST_DATA | 0 | dev_priv->video_device_fuse | 0-u32max |
| HOST_DATA | 0 | dev_priv->vram_stolen_size | 0-u64max |
| HOST_DATA | 0 | *dev_priv | s64min-s64max |
| HALF_LOCKED2 | &pool->lock |
drivers/gpu/drm/gma500/gtt.c psb_gtt_resume() -> psb_gtt_disable()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dev_priv | 4096-ptr_max |
| PARAM_VALUE | 0 | dev_priv->gmch_ctrl | 0 |
| PARAM_VALUE | 0 | dev_priv->gtt.mmu_gatt_start | 3758096384 |
| PARAM_VALUE | 0 | dev_priv->gtt_mem | 4096-ptr_max |
| PARAM_VALUE | 0 | dev_priv->vdc_reg | 4096-ptr_max |
| DATA_SOURCE | 0 | dev_priv | r to_drm_psb_private |
| NOCHECK_CALL | |||
| HOST_DATA | 0 | dev_priv->apm_base | 0-u16max |
| HOST_DATA | 0 | dev_priv->apm_reg | 0-u32max |
| HOST_DATA | 0 | dev_priv->backlight_duty_cycle | s32min-s32max |
| HOST_DATA | 0 | dev_priv->backlight_enabled | 0-1 |
| HOST_DATA | 0 | dev_priv->backlight_level | s32min-s32max |
| HOST_DATA | 0 | dev_priv->blc_adj1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->blc_adj2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->bpp | 0-u32max |
| HOST_DATA | 0 | dev_priv->bpp2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->child_dev_num | s32min-s32max |
| HOST_DATA | 0 | dev_priv->core_freq | 0-u32max |
| HOST_DATA | 0 | dev_priv->crt_ddc_pin | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.clientlist_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.clientlist_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.driver_features | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.filelist_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.filelist_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.gem_lru_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.gem_lru_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.if_version | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.master_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.master_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.max_vblank_count | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.async_page_flip | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.blob_lock.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.blob_lock.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connection_mutex.mutex.base.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connection_mutex.mutex.base.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connector_free_work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.connector_ida.xa.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.cursor_height | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.cursor_width | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.delayed_event | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.fb_lock.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.fb_lock.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.fb_modifiers_not_supported | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.idr_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.idr_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.max_height | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.max_width | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.min_height | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.min_width | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.normalize_zpos | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_colorop | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_connector | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_crtc | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_encoder | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_fb | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.num_total_plane | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.object_idr.idr_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.object_idr.idr_next | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.object_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.cpu | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.timer.expires | 0-u64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.timer.flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.output_poll_work.work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.magic | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.owner_cpu | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.locked | 0-255 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.locked_pending | 0-u16max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.pending | 0-255 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.tail | 0-u16max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.panic_lock.raw_lock.val.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.poll_enabled | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.poll_running | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.prefer_shadow | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.preferred_depth | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.quirk_addfb_prefer_host_byte_order | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.quirk_addfb_prefer_xbgr_30bpp | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.mode_config.tile_idr.idr_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.tile_idr.idr_next | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.mode_config.tile_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.num_crtcs | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_idr.idr_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_idr.idr_next | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_lock.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.object_name_lock.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->dev.open_count.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.ref.refcount.refs.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->dev.registered | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.switch_power_state | 0-u32max |
| HOST_DATA | 0 | dev_priv->dev.unplugged | 0-1 |
| HOST_DATA | 0 | dev_priv->dev.vblank_disable_immediate | 0-1 |
| HOST_DATA | 0 | dev_priv->dplla_96mhz | 0-1 |
| HOST_DATA | 0 | dev_priv->dsr_enable | 0-1 |
| HOST_DATA | 0 | dev_priv->dsr_fb_update | 0-u32max |
| HOST_DATA | 0 | dev_priv->edp.bpp | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.initialized | 0-1 |
| HOST_DATA | 0 | dev_priv->edp.lanes | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.pps.t10 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t11_t12 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t1_t3 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t8 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.pps.t9 | 0-u16max |
| HOST_DATA | 0 | dev_priv->edp.preemphasis | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.rate | s32min-s32max |
| HOST_DATA | 0 | dev_priv->edp.support | 0-1 |
| HOST_DATA | 0 | dev_priv->edp.vswing | s32min-s32max |
| HOST_DATA | 0 | dev_priv->fuse_reg_value | 0-u32max |
| HOST_DATA | 0 | dev_priv->gatt_free_offset | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hactive_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hactive_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hblank_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hblank_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hborder | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.height_mm_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.height_mm_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_offset_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_offset_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_positive | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_pulse_width_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.hsync_pulse_width_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.interlaced | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.pixel_clock | 0-u16max |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.separate_sync | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.stereo | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.unknown0 | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.unknown6 | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vactive_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vactive_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vblank_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vblank_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vborder | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_offset_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_offset_lo | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_positive | 0-1 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_pulse_width_hi | 0-3 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.vsync_pulse_width_lo | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.width_mm_hi | 0-15 |
| HOST_DATA | 0 | dev_priv->gct_data.DTD.width_mm_lo | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.PP_Cycle_Delay | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.PP_Off_Sequencing | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.PP_On_Sequencing | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.Panel_Backlight_Inverter_Descriptor | 0-u16max |
| HOST_DATA | 0 | dev_priv->gct_data.Panel_MIPI_Display_Descriptor | 0-u16max |
| HOST_DATA | 0 | dev_priv->gct_data.Panel_Port_Control | 0-u32max |
| HOST_DATA | 0 | dev_priv->gct_data.bpi | 0-255 |
| HOST_DATA | 0 | dev_priv->gct_data.pt | 0-255 |
| HOST_DATA | 0 | dev_priv->gmch_ctrl | 0 |
| HOST_DATA | 0 | dev_priv->gtt.gtt_phys_start | 0,4096-4294963200 |
| HOST_DATA | 0 | dev_priv->gtt.gtt_start | 0-u32max |
| HOST_DATA | 0 | dev_priv->gtt.stolen_size | 0-u64max |
| HOST_DATA | 0 | dev_priv->gtt.vram_stolen_size | 0-u64max |
| HOST_DATA | 0 | dev_priv->gtt_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->gtt_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->has_gct | 0-1 |
| HOST_DATA | 0 | dev_priv->hotplug_supported_mask | 0-u32max |
| HOST_DATA | 0 | dev_priv->hotplug_work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->iLVDS_enable | 0-u32max |
| HOST_DATA | 0 | dev_priv->int_crt_support | 0-1 |
| HOST_DATA | 0 | dev_priv->int_tv_support | 0-1 |
| HOST_DATA | 0 | dev_priv->irq_enabled | 0-1 |
| HOST_DATA | 0 | dev_priv->is_lvds_on | 0-1 |
| HOST_DATA | 0 | dev_priv->is_mipi_on | 0-1 |
| HOST_DATA | 0 | dev_priv->lpc_gpio_base | 0-u16max |
| HOST_DATA | 0 | dev_priv->lvds_dither | 0-1 |
| HOST_DATA | 0 | dev_priv->lvds_enabled_in_vbt | 0-1 |
| HOST_DATA | 0 | dev_priv->lvds_ssc_freq | s32min-s32max |
| HOST_DATA | 0 | dev_priv->lvds_use_ssc | 0-1 |
| HOST_DATA | 0 | dev_priv->lvds_vbt | 0-1 |
| HOST_DATA | 0 | dev_priv->mipi_ctrl_display | 0-u32max |
| HOST_DATA | 0 | dev_priv->mmap_mutex.osq.tail.counter | s32min-s32max |
| HOST_DATA | 0 | dev_priv->mmap_mutex.owner.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->mode_dev.backlight_duty_cycle | s32min-s32max |
| HOST_DATA | 0 | dev_priv->mode_dev.panel_wants_dither | 0-1 |
| HOST_DATA | 0 | dev_priv->mode_dev.saveBLC_PWM_CTL | 0-u32max |
| HOST_DATA | 0 | dev_priv->modeset | 0-1 |
| HOST_DATA | 0 | dev_priv->num_pipe | 0-u32max |
| HOST_DATA | 0 | dev_priv->opregion.asle_work.data.counter | s64min-s64max |
| HOST_DATA | 0 | dev_priv->ospm_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->panel_type | 0-255 |
| HOST_DATA | 0 | dev_priv->panel_wants_dither | 0-1 |
| HOST_DATA | 0 | dev_priv->pge_ctl | 0-u32max |
| HOST_DATA | 0 | dev_priv->platform_rev_id | 0-255 |
| HOST_DATA | 0 | dev_priv->pm_initialized | 0-1 |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveADPA | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveDSPARB | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveDSPCLK_GATE_D | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveIER | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveIMR | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveLBB | 0-255 |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveLVDS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePFIT_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePFIT_PGM_RATIOS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_CYCLE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_OFF_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.savePP_ON_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveRAMCLK_GATE_D | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.cdv.saveVGACNTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveADPA | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveBCLRPAT_A | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveBCLRPAT_B | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveCHICKENBIT | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveCLOCKGATING | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPACURSOR_BASE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPACURSOR_CTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPACURSOR_POS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPARB | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPBCURSOR_BASE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPBCURSOR_CTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPBCURSOR_POS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW3 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW4 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW5 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDSPFW6 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDVOA | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDVOB | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveDVOC | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveHISTOGRAM_INT_CONTROL_REG | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveHISTOGRAM_LOGIC_CONTROL_REG | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveLVDS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC0 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC3 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC4 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OGAMC5 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOVC_OVADD | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC0 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC3 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC4 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OGAMC5 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveOV_OVADD | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePERF_MODE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePFIT_AUTO_RATIOS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePFIT_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePFIT_PGM_RATIOS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_CONTROL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_CYCLE | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_DIVISOR | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_OFF | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_OFF_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_ON | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePP_ON_DELAYS | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.savePWM_CONTROL_LOGIC | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVCLK_DIVISOR_VGA0 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVCLK_DIVISOR_VGA1 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVCLK_POST_DIV | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.psb.saveVGACNTRL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveBLC_PWM_CTL | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveBLC_PWM_CTL2 | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveBSM | 0-u32max |
| HOST_DATA | 0 | dev_priv->regs.saveVBT | 0-u32max |
| HOST_DATA | 0 | dev_priv->stolen_base | 0-u32max |
| HOST_DATA | 0 | dev_priv->use_msi | 0-1 |
| HOST_DATA | 0 | dev_priv->vdc_irq_mask | 0-u32max |
| HOST_DATA | 0 | dev_priv->video_device_fuse | 0-u32max |
| HOST_DATA | 0 | dev_priv->vram_stolen_size | 0-u64max |
| HOST_DATA | 0 | *dev_priv | s64min-s64max |