Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/i915/display/intel_dmc.c intel_dmc_disable_program() -> pipedmc_clock_gating_wa()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->dmc.dmc | 4096-ptr_max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | *display->irq.pipestat_irq_mask | 0-4294967295 |
| PARAM_VALUE | 0 | *display->power.chv_phy_assert | 0-1 |
| PARAM_VALUE | 1 | enable | 1 |
| DATA_SOURCE | 0 | display | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | display->dmc.dmc->dc6_allowed.dc5_start | 0-u32max |
| HOST_DATA | 0 | display->drm->mode_config.object_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
drivers/gpu/drm/i915/display/intel_dmc.c intel_dmc_disable_program() -> pipedmc_clock_gating_wa()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->dmc.dmc | 4096-ptr_max |
| PARAM_VALUE | 0 | display->psr_dc5_dc6_wa_work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.work.work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | *display->irq.pipestat_irq_mask | 0-4294967295 |
| PARAM_VALUE | 0 | *display->power.chv_phy_assert | 0-1 |
| PARAM_VALUE | 1 | enable | 0 |
| DATA_SOURCE | 0 | display | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | display->dmc.dmc->dc6_allowed.dc5_start | 0-u32max |
| HOST_DATA | 0 | display->drm->mode_config.object_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
drivers/gpu/drm/i915/display/intel_dmc.c intel_dmc_load_program() -> pipedmc_clock_gating_wa()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->dmc.dmc | 4096-ptr_max |
| PARAM_VALUE | 0 | display->drm | 0,4096-ptr_max |
| PARAM_VALUE | 0 | display->drm->mode_config.helper_private->atomic_commit_tail | 0,113,234517204248432640,264416658693812224,1002985563129995264,1135616218159751168,1435312838172803072,1559742614509715456,1682444203744997376,2792895115794366464,3649211429048074240,4264110321136541696,4348468181405868032-s64max |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->parent->rpm | 4096-ptr_max |
| PARAM_VALUE | 0 | display->parent->rpm->assert_held | 4096-ptr_max |
| PARAM_VALUE | 0 | *display->bw.peakbw | 0-4294967295 |
| PARAM_VALUE | 0 | *display->bw.psf_bw | 0-4294967295 |
| PARAM_VALUE | 0 | *display->irq.pipestat_irq_mask | 0-4294967295 |
| PARAM_VALUE | 1 | enable | 1 |
| DATA_SOURCE | 0 | display | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | display->cdclk.hw.cdclk | 0-39168016[c] |
| HOST_DATA | 0 | display->cdclk.hw.joined_mbus | 0-1 |
| HOST_DATA | 0 | display->cdclk.hw.voltage_level | 0-31[c] |
| HOST_DATA | 0 | display->cdclk.max_cdclk_freq | 1-16[c] |
| HOST_DATA | 0 | display->cdclk.max_dotclk_freq | 0-32[c] |
| HOST_DATA | 0 | display->dmc.dmc->dc6_allowed.dc5_start | 0-u32max |
| HOST_DATA | 0 | display->drm->mode_config.object_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | display->hti.state | 0-u32max |
| HOST_DATA | 0 | display->power.domains.dc_state | 0-u32max |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
| NO_OVERFLOW_SIMPLE | 0 | display->drm->num_crtcs |
drivers/gpu/drm/i915/display/intel_dmc.c intel_dmc_load_program() -> pipedmc_clock_gating_wa()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | display | 4096-ptr_max |
| PARAM_VALUE | 0 | display->dmc.dmc | 4096-ptr_max |
| PARAM_VALUE | 0 | display->drm | 0,4096-ptr_max |
| PARAM_VALUE | 0 | display->drm->mode_config.helper_private->atomic_commit_tail | 0,113,234517204248432640,264416658693812224,1002985563129995264,1135616218159751168,1435312838172803072,1559742614509715456,1682444203744997376,2792895115794366464,3649211429048074240,4264110321136541696,4348468181405868032-s64max |
| PARAM_VALUE | 0 | display->params.enable_dmc_wl | 0-1 |
| PARAM_VALUE | 0 | display->parent | 4096-ptr_max |
| PARAM_VALUE | 0 | display->parent->rpm | 4096-ptr_max |
| PARAM_VALUE | 0 | display->parent->rpm->assert_held | 4096-ptr_max |
| PARAM_VALUE | 0 | display->power.domains.dc_state | 0 |
| PARAM_VALUE | 0 | display->wl.taken | 1 |
| PARAM_VALUE | 0 | display->wl.work->timer->entry.pprev | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.work.timer.entry->pprev | 4096-ptr_max |
| PARAM_VALUE | 0 | display->wl.work.work.entry.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | *display->bw.peakbw | 0-4294967295 |
| PARAM_VALUE | 0 | *display->bw.psf_bw | 0-4294967295 |
| PARAM_VALUE | 0 | *display->irq.pipestat_irq_mask | 0-4294967295 |
| PARAM_VALUE | 1 | enable | 0 |
| DATA_SOURCE | 0 | display | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | display->cdclk.hw.cdclk | 0-39168016[c] |
| HOST_DATA | 0 | display->cdclk.hw.joined_mbus | 0-1 |
| HOST_DATA | 0 | display->cdclk.hw.voltage_level | 0-31[c] |
| HOST_DATA | 0 | display->cdclk.max_cdclk_freq | 1-16[c] |
| HOST_DATA | 0 | display->cdclk.max_dotclk_freq | 0-32[c] |
| HOST_DATA | 0 | display->dmc.dmc->dc6_allowed.dc5_start | 0-u32max |
| HOST_DATA | 0 | display->drm->mode_config.object_idr.idr_rt.xa_flags | 0-u32max |
| HOST_DATA | 0 | display->hti.state | 0-u32max |
| HOST_DATA | 0 | display->power.domains.dc_state | 0 |
| HOST_DATA | 0 | display->state.bxt_phy_grc | 0-u32max |
| NO_OVERFLOW_SIMPLE | 0 | display->drm->num_crtcs |