Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 11 files:
- drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
- drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c, line 482
- drivers/gpu/drm/bridge/nwl-dsi.c, line 788
- drivers/gpu/drm/meson/meson_dw_mipi_dsi.c, line 167
- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c, line 597
- drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c, line 162
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c, line 764
- drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c, line 169
- drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c, line 231
- drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c, line 263
- drivers/phy/phy-core-mipi-dphy.c, line 89
Smatch caller information:
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c sun8i_a83t_mipi_csi2_s_stream() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 1-u64max |
| PARAM_VALUE | 2 | lanes | 1-255 |
| PARAM_VALUE | 3 | cfg->clk_miss | 0 |
| PARAM_VALUE | 3 | cfg->clk_post | 0 |
| PARAM_VALUE | 3 | cfg->clk_pre | 0 |
| PARAM_VALUE | 3 | cfg->clk_prepare | 0 |
| PARAM_VALUE | 3 | cfg->clk_settle | 0 |
| PARAM_VALUE | 3 | cfg->clk_term_en | 0 |
| PARAM_VALUE | 3 | cfg->clk_trail | 0 |
| PARAM_VALUE | 3 | cfg->clk_zero | 0 |
| PARAM_VALUE | 3 | cfg->d_term_en | 0 |
| PARAM_VALUE | 3 | cfg->eot | 0 |
| PARAM_VALUE | 3 | cfg->hs_clk_rate | 0 |
| PARAM_VALUE | 3 | cfg->hs_exit | 0 |
| PARAM_VALUE | 3 | cfg->hs_prepare | 0 |
| PARAM_VALUE | 3 | cfg->hs_settle | 0 |
| PARAM_VALUE | 3 | cfg->hs_skip | 0 |
| PARAM_VALUE | 3 | cfg->hs_trail | 0 |
| PARAM_VALUE | 3 | cfg->hs_zero | 0 |
| PARAM_VALUE | 3 | cfg->init | 0 |
| PARAM_VALUE | 3 | cfg->lanes | 0 |
| PARAM_VALUE | 3 | cfg->lpx | 0 |
| PARAM_VALUE | 3 | cfg->ta_get | 0 |
| PARAM_VALUE | 3 | cfg->ta_go | 0 |
| PARAM_VALUE | 3 | cfg->ta_sure | 0 |
| PARAM_VALUE | 3 | cfg->wakeup | 0 |
| BUF_SIZE | 3 | cfg | 112 |
| DATA_SOURCE | 0 | pixel_clock | r v4l2_ctrl_g_ctrl_int64 |
| NOCHECK_CALL | |||
| UNITS | 2 | lanes | unit_byte |
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dw_mipi_dsi_get_lane_mbps() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-s32max,18446744071562067968-u64max |
| PARAM_VALUE | 1 | bpp | 16,18,24,30 |
| DATA_SOURCE | 1 | bpp | r mipi_dsi_pixel_format_to_bpp |
| DATA_SOURCE | 2 | lanes | $3 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &encoder->bridge_chain_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex.mutex |
drivers/gpu/drm/bridge/nwl-dsi.c nwl_dsi_get_dphy_params() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-s32max,18446744071562067968-u64max |
| PARAM_VALUE | 1 | bpp | 16,18,24,30,4294967274 |
| PARAM_VALUE | 2 | lanes | 1-4 |
| FUZZY_MAX | 2 | lanes | 4 |
| HARD_MAX | 2 | lanes | 4 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &first_bridge->encoder->bridge_chain_mutex |
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c imx93_dsi_get_phy_configure_opts() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 1 | bpp | 16,18,24,30 |
| DATA_SOURCE | 1 | bpp | r mipi_dsi_pixel_format_to_bpp |
| DATA_SOURCE | 2 | lanes | $3 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &first_bridge->encoder->bridge_chain_mutex |
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c cdns_dsi_check_conf() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-s32max,18446744071562067968-18446744073709550616 |
| PARAM_VALUE | 1 | bpp | 16,18,24,30,4294967274 |
| BUF_SIZE | 3 | cfg | 112 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| UNITS | 0 | pixel_clock | unit_byte |
| HALF_LOCKED2 | _T->lock |
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c cdns_dsi_round_pclk() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-s32max,18446744071562067968-u64max |
| PARAM_VALUE | 1 | bpp | 16,18,24,30,4294967274 |
| PARAM_VALUE | 3 | cfg->clk_miss | 0 |
| PARAM_VALUE | 3 | cfg->clk_post | 0 |
| PARAM_VALUE | 3 | cfg->clk_pre | 0 |
| PARAM_VALUE | 3 | cfg->clk_prepare | 0 |
| PARAM_VALUE | 3 | cfg->clk_settle | 0 |
| PARAM_VALUE | 3 | cfg->clk_term_en | 0 |
| PARAM_VALUE | 3 | cfg->clk_trail | 0 |
| PARAM_VALUE | 3 | cfg->clk_zero | 0 |
| PARAM_VALUE | 3 | cfg->d_term_en | 0 |
| PARAM_VALUE | 3 | cfg->eot | 0 |
| PARAM_VALUE | 3 | cfg->hs_clk_rate | 0 |
| PARAM_VALUE | 3 | cfg->hs_exit | 0 |
| PARAM_VALUE | 3 | cfg->hs_prepare | 0 |
| PARAM_VALUE | 3 | cfg->hs_settle | 0 |
| PARAM_VALUE | 3 | cfg->hs_skip | 0 |
| PARAM_VALUE | 3 | cfg->hs_trail | 0 |
| PARAM_VALUE | 3 | cfg->hs_zero | 0 |
| PARAM_VALUE | 3 | cfg->init | 0 |
| PARAM_VALUE | 3 | cfg->lanes | 0 |
| PARAM_VALUE | 3 | cfg->lpx | 0 |
| PARAM_VALUE | 3 | cfg->ta_get | 0 |
| PARAM_VALUE | 3 | cfg->ta_go | 0 |
| PARAM_VALUE | 3 | cfg->ta_sure | 0 |
| PARAM_VALUE | 3 | cfg->wakeup | 0 |
| DATA_SOURCE | 0 | pixel_clock | $1 |
| DATA_SOURCE | 1 | bpp | r mipi_dsi_pixel_format_to_bpp |
| BIT_INFO | 1 | bpp | 0x0,0x1f |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | _T->lock |
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c sun6i_mipi_csi2_s_stream() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 1-u64max |
| PARAM_VALUE | 2 | lanes | 1-255 |
| PARAM_VALUE | 3 | cfg->clk_miss | 0 |
| PARAM_VALUE | 3 | cfg->clk_post | 0 |
| PARAM_VALUE | 3 | cfg->clk_pre | 0 |
| PARAM_VALUE | 3 | cfg->clk_prepare | 0 |
| PARAM_VALUE | 3 | cfg->clk_settle | 0 |
| PARAM_VALUE | 3 | cfg->clk_term_en | 0 |
| PARAM_VALUE | 3 | cfg->clk_trail | 0 |
| PARAM_VALUE | 3 | cfg->clk_zero | 0 |
| PARAM_VALUE | 3 | cfg->d_term_en | 0 |
| PARAM_VALUE | 3 | cfg->eot | 0 |
| PARAM_VALUE | 3 | cfg->hs_clk_rate | 0 |
| PARAM_VALUE | 3 | cfg->hs_exit | 0 |
| PARAM_VALUE | 3 | cfg->hs_prepare | 0 |
| PARAM_VALUE | 3 | cfg->hs_settle | 0 |
| PARAM_VALUE | 3 | cfg->hs_skip | 0 |
| PARAM_VALUE | 3 | cfg->hs_trail | 0 |
| PARAM_VALUE | 3 | cfg->hs_zero | 0 |
| PARAM_VALUE | 3 | cfg->init | 0 |
| PARAM_VALUE | 3 | cfg->lanes | 0 |
| PARAM_VALUE | 3 | cfg->lpx | 0 |
| PARAM_VALUE | 3 | cfg->ta_get | 0 |
| PARAM_VALUE | 3 | cfg->ta_go | 0 |
| PARAM_VALUE | 3 | cfg->ta_sure | 0 |
| PARAM_VALUE | 3 | cfg->wakeup | 0 |
| BUF_SIZE | 3 | cfg | 112 |
| DATA_SOURCE | 0 | pixel_clock | r v4l2_ctrl_g_ctrl_int64 |
| NOCHECK_CALL | |||
| UNITS | 2 | lanes | unit_byte |
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c dw_mipi_dsi_get_lane_mbps() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-s32max,18446744071562067968-u64max |
| PARAM_VALUE | 1 | bpp | 16,18,24,30,4294967274 |
| DATA_SOURCE | 1 | bpp | r mipi_dsi_pixel_format_to_bpp |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &encoder->bridge_chain_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex.mutex |
drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c rkisp1_csi_start() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 1-u64max |
| PARAM_VALUE | 2 | lanes | 1-4 |
| BUF_SIZE | 3 | cfg | 112 |
| DATA_SOURCE | 0 | pixel_clock | r v4l2_ctrl_g_ctrl_int64 |
| NOCHECK_CALL | |||
| UNITS | 2 | lanes | unit_byte |
| HALF_LOCKED2 | sd->active_state->lock |
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c sun6i_dsi_encoder_enable() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-s32max,18446744071562067968-u64max |
| PARAM_VALUE | 1 | bpp | 16,18,24,30,4294967274 |
| PARAM_VALUE | 3 | cfg->clk_miss | 0 |
| PARAM_VALUE | 3 | cfg->clk_post | 0 |
| PARAM_VALUE | 3 | cfg->clk_pre | 0 |
| PARAM_VALUE | 3 | cfg->clk_prepare | 0 |
| PARAM_VALUE | 3 | cfg->clk_settle | 0 |
| PARAM_VALUE | 3 | cfg->clk_term_en | 0 |
| PARAM_VALUE | 3 | cfg->clk_trail | 0 |
| PARAM_VALUE | 3 | cfg->clk_zero | 0 |
| PARAM_VALUE | 3 | cfg->d_term_en | 0 |
| PARAM_VALUE | 3 | cfg->eot | 0 |
| PARAM_VALUE | 3 | cfg->hs_clk_rate | 0 |
| PARAM_VALUE | 3 | cfg->hs_exit | 0 |
| PARAM_VALUE | 3 | cfg->hs_prepare | 0 |
| PARAM_VALUE | 3 | cfg->hs_settle | 0 |
| PARAM_VALUE | 3 | cfg->hs_skip | 0 |
| PARAM_VALUE | 3 | cfg->hs_trail | 0 |
| PARAM_VALUE | 3 | cfg->hs_zero | 0 |
| PARAM_VALUE | 3 | cfg->init | 0 |
| PARAM_VALUE | 3 | cfg->lanes | 0 |
| PARAM_VALUE | 3 | cfg->lpx | 0 |
| PARAM_VALUE | 3 | cfg->ta_get | 0 |
| PARAM_VALUE | 3 | cfg->ta_go | 0 |
| PARAM_VALUE | 3 | cfg->ta_sure | 0 |
| PARAM_VALUE | 3 | cfg->wakeup | 0 |
| BUF_SIZE | 3 | cfg | 112 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &pool->lock | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex.mutex |
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c dw_mipi_dsi2_get_lane_mbps() -> phy_mipi_dphy_get_default_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pixel_clock | 0-268435455 |
| PARAM_VALUE | 1 | bpp | 16,18,24,30 |
| DATA_SOURCE | 1 | bpp | r mipi_dsi_pixel_format_to_bpp |
| DATA_SOURCE | 2 | lanes | $3 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &encoder->bridge_chain_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex | ||
| HALF_LOCKED2 | &state->dev->mode_config.connection_mutex.mutex |