Open Menu /

Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd() -> pcie_do_write_cmd()

Type Parameter Key Value
PARAM_VALUE 0 ctrl->pcie->port->dev.power.wakeirq->status 0-4294967295
PARAM_VALUE 0 ctrl->pcie->port->link_bwctrl->cdev 0-s64max
PARAM_VALUE 0 ctrl->pcie->port->subordinate->self->link_bwctrl->cdev (-22),(-19),(-12),0-s64max
PARAM_VALUE 0 ctrl->reset_lock.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ctrl->reset_lock.first_waiter->type 0-1
PARAM_VALUE 0 *ctrl->pcie->port->saved_config_space 0-4294967295
PARAM_VALUE 1 cmd 0,1024,4096,4128
PARAM_VALUE 2 mask 1024,4096,4128,4159
PARAM_VALUE 3 wait 1
BUF_SIZE 0 ctrl (-1),128,168,944,1056
BUF_SIZE 0 ctrl (-1),128,168,944,1056
DATA_SOURCE 0 ctrl $0
DATA_SOURCE 1 cmd $1
DATA_SOURCE 2 mask $2
FUZZY_MAX 1 cmd 4096
FUZZY_MAX 2 mask 4096
BIT_INFO 1 cmd 0x0,0x17ff
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ctrl->dsn 0[c]
HOST_DATA 0 ctrl->pcie->port->current_state 0-3[c]
HOST_DATA 0 ctrl->pcie->port->pcie_flags_reg 0-u16max
HOST_DATA 0 ctrl->slot_cap 0,262144[c]
HOST_DATA 0 ctrl->slot_ctrl 0-u16max[c]
HALF_LOCKED2 0 &ctrl->reset_lock

drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd_nowait() -> pcie_do_write_cmd()

Type Parameter Key Value
PARAM_VALUE 0 ctrl 4096-ptr_max
PARAM_VALUE 0 ctrl->pcie 4096-ptr_max
PARAM_VALUE 0 ctrl->pcie->port->dev.power.wakeirq->status 0-4294967295
PARAM_VALUE 0 ctrl->pcie->port->link_bwctrl->cdev 0-s64max
PARAM_VALUE 0 ctrl->pcie->port->subordinate->self->link_bwctrl->cdev (-22),(-19),(-12),0-s64max
PARAM_VALUE 0 ctrl->reset_lock.first_waiter->handoff_set 0-1
PARAM_VALUE 0 ctrl->reset_lock.first_waiter->type 0-1
PARAM_VALUE 0 *ctrl->pcie->port->saved_config_space 0-4294967295
PARAM_VALUE 1 cmd 0-1023,4097,4104,4129,4136,4145,4152,16384
PARAM_VALUE 2 mask 192,768,960,4155,16384
PARAM_VALUE 3 wait 0
BUF_SIZE 0 ctrl (-1),128,944
BUF_SIZE 0 ctrl (-1),128,944
DATA_SOURCE 0 ctrl $0
DATA_SOURCE 1 cmd $1
DATA_SOURCE 2 mask $2
BIT_INFO 1 cmd 0x0,0x53f9
BIT_INFO 2 mask 0x0,0x53fb
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ctrl->dsn 0[c]
HOST_DATA 0 ctrl->pcie->port->acs_capabilities 0-u16max
HOST_DATA 0 ctrl->pcie->port->bus->bridge_ctl 0-u16max
HOST_DATA 0 ctrl->pcie->port->bus->parent->bridge_ctl 0-u16max
HOST_DATA 0 ctrl->pcie->port->class 0-16777215
HOST_DATA 0 ctrl->pcie->port->current_state 0-3[c]
HOST_DATA 0 ctrl->pcie->port->devcap 0-u32max
HOST_DATA 0 ctrl->pcie->port->devfn 0-503[c]
HOST_DATA 0 ctrl->pcie->port->device 0-u16max
HOST_DATA 0 ctrl->pcie->port->eetlp_prefix_max 0-7[c]
HOST_DATA 0 ctrl->pcie->port->fm_enabled 0-1[c]
HOST_DATA 0 ctrl->pcie->port->hdr_type 0-255[c]
HOST_DATA 0 ctrl->pcie->port->ide_cfg 0-1[c]
HOST_DATA 0 ctrl->pcie->port->ide_tee_limit 0-1[c]
HOST_DATA 0 ctrl->pcie->port->irq 0-255
HOST_DATA 0 ctrl->pcie->port->is_cxl 0-1
HOST_DATA 0 ctrl->pcie->port->multifunction 0-1[c]
HOST_DATA 0 ctrl->pcie->port->nr_ide_mem 0-255[c]
HOST_DATA 0 ctrl->pcie->port->pcie_flags_reg 0-u16max
HOST_DATA 0 ctrl->pcie->port->pcie_mpss 0-7[c]
HOST_DATA 0 ctrl->pcie->port->physfn->acs_capabilities 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->bus->bridge_ctl 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->bus->parent->bridge_ctl 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->class 0-16777215
HOST_DATA 0 ctrl->pcie->port->physfn->current_state 0-3[c]
HOST_DATA 0 ctrl->pcie->port->physfn->devcap 0-u32max
HOST_DATA 0 ctrl->pcie->port->physfn->devfn 1-503[c]
HOST_DATA 0 ctrl->pcie->port->physfn->device 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->eetlp_prefix_max 0-7[c]
HOST_DATA 0 ctrl->pcie->port->physfn->fm_enabled 0-1[c]
HOST_DATA 0 ctrl->pcie->port->physfn->hdr_type 0-255[c]
HOST_DATA 0 ctrl->pcie->port->physfn->ide_cfg 0-1[c]
HOST_DATA 0 ctrl->pcie->port->physfn->ide_tee_limit 0-1[c]
HOST_DATA 0 ctrl->pcie->port->physfn->irq 0-255
HOST_DATA 0 ctrl->pcie->port->physfn->is_cxl 0-1
HOST_DATA 0 ctrl->pcie->port->physfn->multifunction 0-1[c]
HOST_DATA 0 ctrl->pcie->port->physfn->nr_ide_mem 0-255[c]
HOST_DATA 0 ctrl->pcie->port->physfn->pcie_flags_reg 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->pcie_mpss 0-7[c]
HOST_DATA 0 ctrl->pcie->port->physfn->pin 0
HOST_DATA 0 ctrl->pcie->port->physfn->pme_support 0-31[c]
HOST_DATA 0 ctrl->pcie->port->physfn->ptm_granularity 0-255[c]
HOST_DATA 0 ctrl->pcie->port->physfn->revision 0-255
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->class 0-u32max
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->hdr_type 0-255
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->max_VF_buses 0-255[c]
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->offset 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->stride 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->subsystem_device 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->sriov->subsystem_vendor 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->subsystem_device 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->subsystem_vendor 0-u16max
HOST_DATA 0 ctrl->pcie->port->physfn->supported_speeds 0,2-254[c]
HOST_DATA 0 ctrl->pcie->port->physfn->transparent 0[c]
HOST_DATA 0 ctrl->pcie->port->physfn->vendor 0-u16max
HOST_DATA 0 ctrl->pcie->port->pin 0
HOST_DATA 0 ctrl->pcie->port->pme_support 0-31[c]
HOST_DATA 0 ctrl->pcie->port->ptm_granularity 0-255[c]
HOST_DATA 0 ctrl->pcie->port->revision 0-255
HOST_DATA 0 ctrl->pcie->port->sriov->max_VF_buses 0-255[c]
HOST_DATA 0 ctrl->pcie->port->subsystem_device 0-u16max
HOST_DATA 0 ctrl->pcie->port->subsystem_vendor 0-u16max
HOST_DATA 0 ctrl->pcie->port->supported_speeds 0,2-254[c]
HOST_DATA 0 ctrl->pcie->port->transparent 0[c]
HOST_DATA 0 ctrl->pcie->port->vendor 0-u16max
HOST_DATA 0 ctrl->slot_cap 0,262144[c]
HOST_DATA 0 ctrl->slot_ctrl 0-u16max[c]
HOST_DATA 0 *ctrl->pcie->port->dev.driver_data s64min-s64max
HOST_DATA 0 *ctrl->pcie->port->physfn->dev.driver_data s64min-s64max
USER_DATA 1 cmd 0-1023[c]
HALF_LOCKED2 &of->mutex
HALF_LOCKED2 0 &ctrl->reset_lock
HALF_LOCKED2 0 &ctrl->state_lock