| PARAM_VALUE |
0 |
nn |
4096-ptr_max |
| CAPPED_DATA |
0 |
nn |
1 |
| CAPPED_DATA |
0 |
nn->dp.num_r_vecs |
1 |
| CAPPED_DATA |
0 |
nn->dp.num_rx_rings |
1 |
| CAPPED_DATA |
0 |
nn->dp.num_tx_rings |
1 |
| CAPPED_DATA |
1 |
idx |
1 |
| DATA_SOURCE |
0 |
nn |
$0 |
| PARAM_COMPARE |
0 |
nn->dp.num_r_vecs |
> $1 |
| PARAM_COMPARE |
1 |
idx |
< $0->dp.num_r_vecs |
| BIT_INFO |
0 |
nn->cap |
0x0,0xffffffff |
| NOSPEC |
0 |
nn->dp.netdev->real_num_rx_queues |
|
| NOSPEC |
0 |
nn->dp.num_tx_rings |
|
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| NOCHECK_CALL |
|
|
|
| HOST_DATA |
0 |
nn->cap |
0-u32max |
| HOST_DATA |
0 |
nn->cap_w1 |
0-u32max |
| HOST_DATA |
0 |
nn->dp.ctrl |
0-u32max[c] |
| HOST_DATA |
0 |
nn->dp.mtu |
0-s32max[c] |
| HOST_DATA |
0 |
nn->dp.netdev->num_napi_configs |
1-u32max |
| HOST_DATA |
0 |
nn->dp.netdev->num_rx_queues |
1-u32max[c] |
| HOST_DATA |
0 |
nn->dp.netdev->num_tx_queues |
1-u16max[c] |
| HOST_DATA |
0 |
nn->dp.netdev->priv_len |
0,8,12,16,24,32,40,48,64,80,104,112,128,144,152,168,216,224,232 |
| HOST_DATA |
0 |
nn->dp.netdev->real_num_rx_queues |
1-u32max |
| HOST_DATA |
0 |
nn->dp.netdev->real_num_tx_queues |
1-u16max |
| HOST_DATA |
0 |
nn->dp.num_r_vecs |
1-s32max[c] |
| HOST_DATA |
0 |
nn->dp.num_rx_rings |
0-s32max[c] |
| HOST_DATA |
0 |
nn->dp.num_tx_rings |
0-s32max[c] |
| HOST_DATA |
0 |
nn->dp.rx_offset |
0-64 |
| HOST_DATA |
0 |
nn->max_mtu |
0-u32max |
| HOST_DATA |
0 |
nn->max_r_vecs |
0-s32max[c] |
| HOST_DATA |
0 |
nn->max_rx_rings |
0-u32max |
| HOST_DATA |
0 |
nn->max_tx_rings |
0-u32max |
| HOST_DATA |
0 |
nn->pdev->current_state |
0-3[c] |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.flavour |
0-2,4-7 |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.lanes |
0-u32max |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.no_phys_port_name |
0-1 |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.pci_sf.sf |
0-u32max |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.pci_vf.vf |
0-u16max |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.phys.port_number |
0-u32max |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.phys.split_subport_number |
0-u32max |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.split |
0-1 |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.splittable |
0-1 |
| HOST_DATA |
0 |
nn->port->dl_port.attrs.switch_id.id_len |
0-32 |
| HOST_DATA |
0 |
nn->tlv_caps.crypto_enable_off |
0 |
| HOST_DATA |
0 |
nn->tlv_caps.crypto_ops |
0-u32max |
| HOST_DATA |
0 |
nn->tlv_caps.mbox_cmsg_types |
0-u32max |
| HOST_DATA |
0 |
nn->tlv_caps.mbox_len |
504 |
| HOST_DATA |
0 |
nn->tlv_caps.mbox_off |
6144 |
| HOST_DATA |
0 |
nn->tlv_caps.me_freq_mhz |
0-u32max |
| HOST_DATA |
0 |
nn->tlv_caps.repr_cap |
0-u32max |
| HOST_DATA |
0 |
nn->tlv_caps.tls_resync_ss |
0 |
| HOST_DATA |
0 |
nn->tlv_caps.vnic_stats_cnt |
0 |
| HOST_DATA |
0 |
nn->tlv_caps.vnic_stats_off |
0 |
| USER_DATA |
0 |
nn->dp.mtu |
0-s32max[c] |
| USER_DATA |
0 |
nn->dp.netdev->mtu |
0-s32max[c] |
| USER_DATA |
0 |
nn->dp.netdev->real_num_rx_queues |
1-s32max[c] |
| USER_DATA |
0 |
nn->dp.num_tx_rings |
0[c] |
| NO_OVERFLOW_SIMPLE |
0 |
nn->dp.num_stack_tx_rings |
|
| NO_OVERFLOW_SIMPLE |
0 |
nn->max_r_vecs |
|
| NO_OVERFLOW_SIMPLE |
0 |
nn->port->dl_port.attrs.phys.port_number |
|
| NO_OVERFLOW_SIMPLE |
0 |
nn->port->netdev->dev_port |
|
| UNITS |
1 |
idx |
unit_array_size |
| HALF_LOCKED2 |
|
&devlink->lock |
|
| HALF_LOCKED2 |
|
global &rtnl_mutex |
|