| PARAM_VALUE |
0 |
pf |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->cpp |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->ctrl_vnic->dp.ops->cap_mask |
4226137727,4226268927 |
| PARAM_VALUE |
0 |
pf->data_vnic_bar |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->dev_info |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->eth_tbl->ports |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->hwinfo |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->mac_stats_mem |
0-ptr_max |
| PARAM_VALUE |
0 |
pf->max_data_vnics |
0-s32max |
| PARAM_VALUE |
0 |
pf->num_vfs |
0-u16max |
| PARAM_VALUE |
0 |
pf->pdev |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->ports.next |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->qc_area |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->rtbl |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->rtbl->cpp->resource_lock.owner |
(-1) |
| PARAM_VALUE |
0 |
pf->rtbl->num |
s32min-s32max |
| PARAM_VALUE |
0 |
pf->unload_fw_on_remove |
1 |
| PARAM_VALUE |
0 |
pf->vf_cfg_mem |
0-ptr_max |
| PARAM_VALUE |
0 |
pf->vfcfg_tbl2 |
0-ptr_max |
| PARAM_VALUE |
0 |
pf->vnics.next |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->vnics.prev |
4096-ptr_max |
| PARAM_VALUE |
0 |
pf->wq |
4096-ptr_max |
| PARAM_VALUE |
1 |
abm |
4096-ptr_max |
| PARAM_VALUE |
1 |
abm->prio_map_len |
0-4000000 |
| PARAM_VALUE |
2 |
nn |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app->cpp |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app->ctrl_mtu |
0 |
| PARAM_VALUE |
2 |
nn->app->pdev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app->pf |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app->priv |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app->type |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->app_priv |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dev_info |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dev_info->dma_mask |
1099511627775,281474976710655 |
| PARAM_VALUE |
2 |
nn->dev_info->max_qc_size |
65536,262144 |
| PARAM_VALUE |
2 |
nn->dev_info->min_qc_size |
256,512 |
| PARAM_VALUE |
2 |
nn->dev_info->pcie_cfg_expbar_offset |
0,1024,2560 |
| PARAM_VALUE |
2 |
nn->dev_info->pcie_expl_offset |
0,4096,53248 |
| PARAM_VALUE |
2 |
nn->dev_info->qc_addr_offset |
0,524288,4194304 |
| PARAM_VALUE |
2 |
nn->dev_info->qc_area_sz |
0,524288,1048576 |
| PARAM_VALUE |
2 |
nn->dev_info->qc_idx_mask |
255,511 |
| PARAM_VALUE |
2 |
nn->dp.ctrl_bar |
1-u64max |
| PARAM_VALUE |
2 |
nn->dp.dev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dp.dev->dma_mask |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dp.dev->driver_data |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dp.is_vf |
0 |
| PARAM_VALUE |
2 |
nn->dp.netdev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dp.netdev->dev.parent |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->dp.ops |
391473416707108864,9078669766065852416 |
| PARAM_VALUE |
2 |
nn->dp.rxd_cnt |
4096 |
| PARAM_VALUE |
2 |
nn->dp.txd_cnt |
4096 |
| PARAM_VALUE |
2 |
nn->dp.xsk_pools |
16,4096-ptr_max |
| PARAM_VALUE |
2 |
nn->fw_ver.major |
5-255 |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.queue.next |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.queue.prev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.queue.qlen |
0 |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.workq |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.wq.head.next |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.wq.head.next->next |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.wq.head.prev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.wq.head.prev->next |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->mbox_cmsg.wq.head.prev->prev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->pdev |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->pdev->dev.dma_mask |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->pdev->dev.driver_data |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->pdev->driver |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->pdev->error_state |
0-2,4-u32max |
| PARAM_VALUE |
2 |
nn->pdev->is_busmaster |
1 |
| PARAM_VALUE |
2 |
nn->pdev->pcie_cap |
0-1 |
| PARAM_VALUE |
2 |
nn->reconfig_timer.entry.pprev |
0 |
| PARAM_VALUE |
2 |
nn->reconfig_timer.flags |
0-4194302 |
| PARAM_VALUE |
2 |
nn->reconfig_timer.lockdep_map->name |
0-255 |
| PARAM_VALUE |
2 |
nn->rx_bar |
4096-ptr_max |
| PARAM_VALUE |
2 |
nn->stride_rx |
2,4 |
| PARAM_VALUE |
2 |
nn->stride_tx |
2,4 |
| PARAM_VALUE |
2 |
nn->tlv_caps.mbox_len |
0,504 |
| PARAM_VALUE |
2 |
nn->tlv_caps.mbox_off |
0,6144 |
| PARAM_VALUE |
2 |
nn->tx_bar |
4096-ptr_max |
| PARAM_VALUE |
3 |
id |
0-2147483646 |
| BUF_SIZE |
1 |
abm |
104,8928,14072 |
| BUF_SIZE |
1 |
abm |
104,8928,14072 |
| BUF_SIZE |
2 |
nn->app |
(-1),104 |
| BUF_SIZE |
2 |
nn->app_priv |
168 |
| BUF_SIZE |
2 |
nn->pdev |
(-1),1-s32max |
| CAPPED_DATA |
0 |
pf->max_data_vnics |
1 |
| CAPPED_DATA |
0 |
pf->num_vfs |
1 |
| CAPPED_DATA |
2 |
nn->dp.num_r_vecs |
1 |
| CAPPED_DATA |
2 |
nn->dp.num_rx_rings |
1 |
| CAPPED_DATA |
2 |
nn->dp.num_tx_rings |
1 |
| CAPPED_DATA |
2 |
nn->max_r_vecs |
1 |
| CAPPED_DATA |
3 |
id |
1 |
| DATA_SOURCE |
2 |
nn |
$1 |
| DATA_SOURCE |
3 |
id |
$2 |
| FUZZY_MAX |
2 |
nn->stride_rx |
4 |
| FUZZY_MAX |
2 |
nn->stride_tx |
4 |
| BIT_INFO |
2 |
nn->dp.ops |
0x56cca0d05451000,0xffffffffffffffff |
| BIT_INFO |
2 |
nn->stride_rx |
0x0,0x6 |
| BIT_INFO |
2 |
nn->stride_tx |
0x0,0x6 |
| HARD_MAX |
2 |
nn->stride_rx |
4 |
| HARD_MAX |
2 |
nn->stride_tx |
4 |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| NOCHECK_CALL |
|
|
|
| HOST_DATA |
2 |
nn->dp.num_r_vecs |
0-s32max[c] |
| HOST_DATA |
2 |
nn->dp.num_rx_rings |
0-s32max[c] |
| HOST_DATA |
2 |
nn->dp.num_tx_rings |
0-s32max[c] |
| HOST_DATA |
2 |
nn->max_r_vecs |
0-s32max[c] |
| HOST_DATA |
2 |
nn->max_rx_rings |
0-u32max |
| HOST_DATA |
2 |
nn->max_tx_rings |
0-u32max |
| HOST_DATA |
2 |
nn->pdev->current_state |
0-3[c] |
| HOST_DATA |
2 |
nn->tlv_caps.crypto_enable_off |
0 |
| HOST_DATA |
2 |
nn->tlv_caps.crypto_ops |
0-u32max |
| HOST_DATA |
2 |
nn->tlv_caps.mbox_cmsg_types |
0-u32max |
| HOST_DATA |
2 |
nn->tlv_caps.mbox_len |
504 |
| HOST_DATA |
2 |
nn->tlv_caps.mbox_off |
6144 |
| HOST_DATA |
2 |
nn->tlv_caps.me_freq_mhz |
0-u32max |
| HOST_DATA |
2 |
nn->tlv_caps.repr_cap |
0-u32max |
| HOST_DATA |
2 |
nn->tlv_caps.tls_resync_ss |
0 |
| HOST_DATA |
2 |
nn->tlv_caps.vnic_stats_cnt |
0 |
| HOST_DATA |
2 |
nn->tlv_caps.vnic_stats_off |
0 |
| NO_OVERFLOW_SIMPLE |
2 |
nn->max_r_vecs |
|
| LOCK2 |
|
&devlink->lock |
|
| TYPE_LOCK |
|
(struct devlink)->lock |
|