Defined in 13 files as a macro:
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h,
line 6025
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h,
line 6102
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h,
line 7776
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h,
line 570
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h,
line 4390
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h,
line 5142
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h,
line 404
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h,
line 48
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h,
line 108
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h,
line 30
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h,
line 164
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h,
line 48
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h,
line 33
(as a macro)
Referenced in 5 files:
