Defined in 14 files as a macro:
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h,
line 1225
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h,
line 1036
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h,
line 1114
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h,
line 840
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h,
line 1138
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h,
line 1076
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h,
line 642
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h,
line 290
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h,
line 124
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h,
line 280
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h,
line 272
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h,
line 324
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h,
line 274
(as a macro)
-
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h,
line 211
(as a macro)
Referenced in 3 files:
