Defined in 3 files as a macro:
- drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h, line 67 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h, line 38 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h, line 208 (as a macro)