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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/meson/meson_viu.c meson_viu_init() -> meson_viu_load_matrix()

Type Parameter Key Value
PARAM_VALUE 0 priv 4096-ptr_max
BUF_SIZE 0 priv s32min-(-2),1-s32max
BUF_SIZE 0 priv s32min-(-2),1-s32max
BUF_SIZE 0 priv->canvas s32min-(-1),1-s32max
BUF_SIZE 0 priv->drm (-1),3696
BUF_SIZE 0 priv->limits (-1)-0,8
BUF_SIZE 0 priv->vsync_irq s32min-(-1),1-s32max
CAPPED_DATA 0 priv->hhi->volatile_table->n_no_ranges 1
CAPPED_DATA 0 priv->hhi->volatile_table->n_yes_ranges 1
DATA_SOURCE 0 priv $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
UNITS 0 priv unit_byte

drivers/gpu/drm/meson/meson_viu.c meson_viu_osd1_reset() -> meson_viu_load_matrix()

Type Parameter Key Value
PARAM_VALUE 0 priv 4096-ptr_max
PARAM_VALUE 0 priv->viu.osd_sc_ctrl0 0,12
PARAM_VALUE 0 priv->viu.osd_sc_h_ctrl0 0,4194304-4195327
PARAM_VALUE 0 priv->viu.osd_sc_v_ini_phase 0,65536-4294901760
DATA_SOURCE 0 priv $0
FUZZY_MAX 0 priv->viu.osd_sc_ctrl0 12
FUZZY_MAX 0 priv->viu.osd_sc_h_ctrl0 0
FUZZY_MAX 0 priv->viu.osd_sc_v_ini_phase 0
BIT_INFO 0 priv->viu.osd_sc_ctrl0 0x0,0xc
BIT_INFO 0 priv->viu.osd_sc_h_ctrl0 0x0,0x4003ff
BIT_INFO 0 priv->viu.osd_sc_v_ctrl0 0x0,0x183ffff
BIT_INFO 0 priv->viu.osd_sc_v_ini_phase 0x0,0xffff0000
HARD_MAX 0 priv->viu.osd_sc_ctrl0 12
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 priv->viu->osb_blend0_size 0-u32max
HOST_DATA 0 priv->viu->osb_blend1_size 0-u32max
HOST_DATA 0 priv->viu->osd1_addr 0-u32max
HOST_DATA 0 priv->viu->osd1_afbcd 0-1
HOST_DATA 0 priv->viu->osd1_blk1_cfg4 0-u32max
HOST_DATA 0 priv->viu->osd1_blk2_cfg4 0-u32max
HOST_DATA 0 priv->viu->osd1_commit 0-1
HOST_DATA 0 priv->viu->osd1_ctrl_stat 0-u32max
HOST_DATA 0 priv->viu->osd1_ctrl_stat2 0-u32max
HOST_DATA 0 priv->viu->osd1_enabled 0-1
HOST_DATA 0 priv->viu->osd1_height 0-u32max
HOST_DATA 0 priv->viu->osd1_interlace 0-1
HOST_DATA 0 priv->viu->osd1_stride 0-u32max
HOST_DATA 0 priv->viu->osd1_width 0-u32max
HOST_DATA 0 priv->viu->osd_blend_din0_scope_h 0-u32max
HOST_DATA 0 priv->viu->osd_blend_din0_scope_v 0-u32max
HOST_DATA 0 priv->viu->osd_sc_ctrl0 0-u32max
HOST_DATA 0 priv->viu->osd_sc_h_ctrl0 0-u32max
HOST_DATA 0 priv->viu->osd_sc_h_ini_phase 0-u32max
HOST_DATA 0 priv->viu->osd_sc_h_phase_step 0-u32max
HOST_DATA 0 priv->viu->osd_sc_i_wh_m1 0-u32max
HOST_DATA 0 priv->viu->osd_sc_o_h_start_end 0-u32max
HOST_DATA 0 priv->viu->osd_sc_o_v_start_end 0-u32max
HOST_DATA 0 priv->viu->osd_sc_v_ctrl0 0-u32max
HOST_DATA 0 priv->viu->osd_sc_v_ini_phase 0-u32max
HOST_DATA 0 priv->viu->osd_sc_v_phase_step 0-u32max
HOST_DATA 0 priv->viu->vd1_addr0 0-u32max
HOST_DATA 0 priv->viu->vd1_addr1 0-u32max
HOST_DATA 0 priv->viu->vd1_addr2 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc 0-1
HOST_DATA 0 priv->viu->vd1_afbc_body_addr 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_conv_ctrl 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_dec_def_color 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_en 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_head_addr 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_mif_hor_scope 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_mif_ver_scope 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_mode 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_pixel_hor_scope 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_pixel_ver_scope 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_size_in 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_size_out 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_vd_cfmt_ctrl 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_vd_cfmt_h 0-u32max
HOST_DATA 0 priv->viu->vd1_afbc_vd_cfmt_w 0-u32max
HOST_DATA 0 priv->viu->vd1_commit 0-1
HOST_DATA 0 priv->viu->vd1_enabled 0-1
HOST_DATA 0 priv->viu->vd1_height0 0-u32max
HOST_DATA 0 priv->viu->vd1_height1 0-u32max
HOST_DATA 0 priv->viu->vd1_height2 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_canvas0 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_chroma0_rpt_pat 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_chroma_x0 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_chroma_y0 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_gen_reg 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_gen_reg2 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_luma0_rpt_pat 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_luma_x0 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_luma_y0 0-u32max
HOST_DATA 0 priv->viu->vd1_if0_repeat_loop 0-u32max
HOST_DATA 0 priv->viu->vd1_planes 0-u32max
HOST_DATA 0 priv->viu->vd1_range_map_cb 0-u32max
HOST_DATA 0 priv->viu->vd1_range_map_cr 0-u32max
HOST_DATA 0 priv->viu->vd1_range_map_y 0-u32max
HOST_DATA 0 priv->viu->vd1_stride0 0-u32max
HOST_DATA 0 priv->viu->vd1_stride1 0-u32max
HOST_DATA 0 priv->viu->vd1_stride2 0-u32max
HOST_DATA 0 priv->viu->viu_vd1_fmt_ctrl 0-u32max
HOST_DATA 0 priv->viu->viu_vd1_fmt_w 0-u32max
HOST_DATA 0 priv->viu->vpp_blend_vd2_h_start_end 0-u32max
HOST_DATA 0 priv->viu->vpp_blend_vd2_v_start_end 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_phase_ctrl 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_region12_startp 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_region1_phase_slope 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_region34_startp 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_region3_phase_slope 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_region4_endp 0-u32max
HOST_DATA 0 priv->viu->vpp_hsc_start_phase_step 0-u32max
HOST_DATA 0 priv->viu->vpp_line_in_length 0-u32max
HOST_DATA 0 priv->viu->vpp_pic_in_height 0-u32max
HOST_DATA 0 priv->viu->vpp_postblend_vd1_h_start_end 0-u32max
HOST_DATA 0 priv->viu->vpp_postblend_vd1_v_start_end 0-u32max
HOST_DATA 0 priv->viu->vpp_preblend_h_size 0-u32max
HOST_DATA 0 priv->viu->vpp_vsc_ini_phase 0-u32max
HOST_DATA 0 priv->viu->vpp_vsc_phase_ctrl 0-u32max
HOST_DATA 0 priv->viu->vpp_vsc_region12_startp 0-u32max
HOST_DATA 0 priv->viu->vpp_vsc_region34_startp 0-u32max
HOST_DATA 0 priv->viu->vpp_vsc_region4_endp 0-u32max
HOST_DATA 0 priv->viu->vpp_vsc_start_phase_step 0-u32max
LOCK2 flags
LOCK2 0 &priv->drm->event_lock
HALF_LOCKED2 irq
TYPE_LOCK (struct drm_device)->event_lock