Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c calculate_lowest_supported_state_for_temp_read() -> map_dc_state_into_dml_display_cfg()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal | 0 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 2 | dml_dispcfg | 4096-ptr_max |
| CAPPED_DATA | 0 | dml2->config.dcn_pipe_count | 1 |
| DATA_SOURCE | 0 | dml2 | $0 |
| DATA_SOURCE | 1 | context | $1 |
| MEM_ZERO | 2 | dml_dispcfg | |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c dml2_validate_only() -> map_dc_state_into_dml_display_cfg()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal | 0 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.dml2 | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 1 | context->stream_count | 1-255 |
| PARAM_VALUE | 2 | dml_dispcfg | 4096-ptr_max |
| DATA_SOURCE | 1 | context | $0 |
| MEM_ZERO | 0 | &dml2->v20.dml_core_ctx.mp | |
| MEM_ZERO | 0 | &dml2->v20.dml_core_ctx.ms | |
| MEM_ZERO | 0 | &dml2->v20.dml_core_ctx.policy | |
| MEM_ZERO | 0 | &dml2->v20.scratch | |
| MEM_ZERO | 2 | dml_dispcfg | |
| PREEMPT_ADD | |||
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_wrapper_fpu.c dml_mode_support_wrapper() -> map_dc_state_into_dml_display_cfg()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dml2 | 4096-ptr_max |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ImmediateFlipRequirement | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->MPCCombineUse | 2 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy->ODMUse | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal | 0 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.DRAMClockChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.FCLKChangeRequirementFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.SynchronizeTimingsFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.USRRetrainingRequiredFinal | 1 |
| PARAM_VALUE | 0 | dml2->v20.dml_core_ctx.policy.UseOnlyMaxPrefetchModes | 1 |
| PARAM_VALUE | 2 | dml_dispcfg | 4096-ptr_max |
| CAPPED_DATA | 0 | dml2->config.dcn_pipe_count | 1 |
| DATA_SOURCE | 0 | dml2 | $0 |
| DATA_SOURCE | 1 | context | $1 |
| MEM_ZERO | 2 | dml_dispcfg | |
| NOCHECK_CALL |