| PARAM_VALUE |
0 |
phba |
4096-ptr_max |
| PARAM_VALUE |
0 |
phba->sli4_hba.CQDBregaddr |
4096-ptr_max |
| PARAM_VALUE |
0 |
phba->sli4_hba.EQDBregaddr |
4096-ptr_max |
| PARAM_VALUE |
0 |
phba->sli4_hba.MQDBregaddr |
4096-ptr_max |
| PARAM_VALUE |
0 |
phba->sli4_hba.RQDBregaddr |
4096-ptr_max |
| PARAM_VALUE |
0 |
phba->sli4_hba.WQDBregaddr |
4096-ptr_max |
| PARAM_VALUE |
0 |
phba->sli4_hba.drbl_regs_memmap_p |
4096-ptr_max |
| PARAM_VALUE |
1 |
vf |
0 |
| BUF_SIZE |
0 |
phba |
78608 |
| BUF_SIZE |
0 |
phba->pcidev |
(-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| CAPPED_DATA |
0 |
phba->pcidev |
1 |
| DATA_SOURCE |
0 |
phba |
$0 |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| HOST_DATA |
0 |
phba->pcidev->acs_capabilities |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->bus->parent->bridge_ctl |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->class |
0-16777215 |
| HOST_DATA |
0 |
phba->pcidev->current_state |
0-3[c] |
| HOST_DATA |
0 |
phba->pcidev->devcap |
0-u32max |
| HOST_DATA |
0 |
phba->pcidev->device |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->eetlp_prefix_max |
0-7[c] |
| HOST_DATA |
0 |
phba->pcidev->fm_enabled |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->hdr_type |
0-255[c] |
| HOST_DATA |
0 |
phba->pcidev->ide_cfg |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->ide_tee_limit |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->irq |
0-255 |
| HOST_DATA |
0 |
phba->pcidev->is_cxl |
0-1 |
| HOST_DATA |
0 |
phba->pcidev->multifunction |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->nr_ide_mem |
0-255[c] |
| HOST_DATA |
0 |
phba->pcidev->pcie_mpss |
0-7[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->acs_capabilities |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->physfn->bus->bridge_ctl |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->physfn->class |
0-16777215 |
| HOST_DATA |
0 |
phba->pcidev->physfn->current_state |
0-3[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->devcap |
0-u32max |
| HOST_DATA |
0 |
phba->pcidev->physfn->devfn |
1-503[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->device |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->physfn->eetlp_prefix_max |
0-7[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->fm_enabled |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->hdr_type |
0-255[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->ide_cfg |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->ide_tee_limit |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->irq |
0-255 |
| HOST_DATA |
0 |
phba->pcidev->physfn->is_cxl |
0-1 |
| HOST_DATA |
0 |
phba->pcidev->physfn->multifunction |
0-1[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->nr_ide_mem |
0-255[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->pcie_flags_reg |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->physfn->pcie_mpss |
0-7[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->pin |
0 |
| HOST_DATA |
0 |
phba->pcidev->physfn->pme_support |
0-31[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->ptm_granularity |
0-255[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->revision |
0-255 |
| HOST_DATA |
0 |
phba->pcidev->physfn->subsystem_device |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->physfn->subsystem_vendor |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->physfn->supported_speeds |
0,2-254[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->transparent |
0[c] |
| HOST_DATA |
0 |
phba->pcidev->physfn->vendor |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->pin |
0 |
| HOST_DATA |
0 |
phba->pcidev->pme_support |
0-31[c] |
| HOST_DATA |
0 |
phba->pcidev->ptm_granularity |
0-255[c] |
| HOST_DATA |
0 |
phba->pcidev->revision |
0-255 |
| HOST_DATA |
0 |
phba->pcidev->subsystem_device |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->subsystem_vendor |
0-u16max |
| HOST_DATA |
0 |
phba->pcidev->supported_speeds |
0,2-254[c] |
| HOST_DATA |
0 |
phba->pcidev->transparent |
0[c] |
| HOST_DATA |
0 |
phba->pcidev->vendor |
0-u16max |
| HOST_DATA |
0 |
phba->sli4_hba.asic_id.word0 |
0 |
| HOST_DATA |
0 |
phba->sli4_hba.sli_intf.word0 |
0 |
| HOST_DATA |
0 |
*phba->pcidev->dev.driver_data |
s64min-s64max |
| HOST_DATA |
0 |
*phba->pcidev->physfn->dev.driver_data |
s64min-s64max |
| HALF_LOCKED2 |
|
&pdev->dev.mutex |
|
| HALF_LOCKED2 |
|
&pool->lock |
|