| PARAM_VALUE |
0 |
ctx_buf |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->ctxbuf |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->ctxbuf->context |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->entry_cnt |
1 |
| PARAM_VALUE |
0 |
ctx_buf->context->flag |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->hdwq |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->list.next |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->offset |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->phba |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->phba->nvmet_support |
1-255 |
| PARAM_VALUE |
0 |
ctx_buf->context->phba->sli4_hba.nvmet_cqset |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->phba->sli4_hba.nvmet_mrq_data |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->phba->sli4_hba.nvmet_mrq_hdr |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->phba->sli4_hba.t_active_ctx_list.prev |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->phba->targetport |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->rqb_buffer |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->rqb_buffer->hbuf.virt |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->context->sid |
0-16777215 |
| PARAM_VALUE |
0 |
ctx_buf->context->state |
4 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_cmd_nvme |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_data_nvme |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_data_wqput |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_isr_data |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_isr_status |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_nvme_data |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_nvme_status |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_status_nvme |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->ts_status_wqput |
0 |
| PARAM_VALUE |
0 |
ctx_buf->context->wqeq |
0 |
| PARAM_VALUE |
0 |
ctx_buf->list.next->prev |
4096-ptr_max |
| PARAM_VALUE |
0 |
ctx_buf->list.prev->next |
4096-ptr_max |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| NOCHECK_CALL |
|
|
|
| HALF_LOCKED2 |
|
&pool->lock |
|