kfd_set_dbg_ev_from_interrupt identifier - Linux source code next-20260811

Projects

linux

Versions

FIXME
- FIXME
  - next-20260811

Defined in 1 files as a prototype:

drivers/gpu/drm/amd/amdkfd/kfd_debug.h, line 35 (as a prototype)

Defined in 1 files as a function:

drivers/gpu/drm/amd/amdkfd/kfd_debug.c, line 199 (as a function)

Referenced in 4 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c event_interrupt_wq_v9() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	3	trap_mask	0-511
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c event_interrupt_wq_v9() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c event_interrupt_wq_v9() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	u32max
PARAM_VALUE	3	trap_mask	4294967296
PARAM_VALUE	4	exception_data	9016749675996540928
PARAM_VALUE	5	exception_data_size	32
BUF_SIZE	4	exception_data	32
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
MEM_ZERO	4	exception_data
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
UNITS	5	exception_data_size	unit_byte
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.c event_interrupt_wq_v10() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	3	trap_mask	0-511
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.c event_interrupt_wq_v10() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.c event_interrupt_wq_v10() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	u32max
PARAM_VALUE	3	trap_mask	4294967296
PARAM_VALUE	4	exception_data	3217895231135105024
PARAM_VALUE	5	exception_data_size	32
BUF_SIZE	4	exception_data	32
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
MEM_ZERO	4	exception_data
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
UNITS	5	exception_data_size	unit_byte
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.c event_interrupt_wq_v11() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	u32max
PARAM_VALUE	3	trap_mask	4294967296
PARAM_VALUE	4	exception_data	6047574357337518080
PARAM_VALUE	5	exception_data_size	32
BUF_SIZE	4	exception_data	32
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
MEM_ZERO	4	exception_data
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
UNITS	5	exception_data_size	unit_byte
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.c event_interrupt_wq_v11() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.c event_interrupt_wq_v11() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	3	trap_mask	0-16383
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v12_1.c event_interrupt_wq_v12_1() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	u32max
PARAM_VALUE	3	trap_mask	4294967296
PARAM_VALUE	4	exception_data	1321126365252558848
PARAM_VALUE	5	exception_data_size	32
BUF_SIZE	4	exception_data	32
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
MEM_ZERO	4	exception_data
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
UNITS	5	exception_data_size	unit_byte
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v12_1.c event_interrupt_wq_v12_1() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
NOCHECK_CALL
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v12_1.c event_interrupt_wq_v12_1() -> kfd_set_dbg_ev_from_interrupt()

Type	Parameter	Key	Value
PARAM_VALUE	0	dev	4096-ptr_max
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->handoff_set	0-1
PARAM_VALUE	0	dev->adev->reset_domain->sem.first_waiter->type	0-1
PARAM_VALUE	0	dev->kfd	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.event_interrupt_class	4096-ptr_max
PARAM_VALUE	0	dev->kfd->device_info.ih_ring_entry_size	0-s32max,18446744071562067968-u64max
PARAM_VALUE	2	doorbell_id	0-1023
PARAM_VALUE	3	trap_mask	0-16383
PARAM_VALUE	4	exception_data	0
PARAM_VALUE	5	exception_data_size	0
CAPPED_DATA	0	dev	1
CAPPED_DATA	0	dev->kfd->device_info.ih_ring_entry_size	1
DATA_SOURCE	0	dev	$0
HOST_DATA	0	dev->adev->virt.fw_reserve.checksum_key	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.offset	0-u32max
HOST_DATA	0	dev->adev->virt.init_data_header.size_kb	0-u32max
HALF_LOCKED2		&pool->lock