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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c jpeg_v1_0_decode_ring_set_patch_ring() -> jpeg_v1_0_decode_ring_patch_wreg()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->reg_offset 4096-ptr_max
PARAM_VALUE 2 reg_offset 0,4-4294967292
BUF_SIZE 0 ring 13600
BUF_SIZE 0 ring 13600
DATA_SOURCE 0 ring $0
BIT_INFO 2 reg_offset 0x0,0xfffffffc
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->wptr 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &vinst->vcn_pg_lock

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c jpeg_v1_0_decode_ring_set_patch_ring() -> jpeg_v1_0_decode_ring_patch_wreg()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 ring->ring 4096-ptr_max
PARAM_VALUE 1 ptr 4096-ptr_max
PARAM_VALUE 2 reg_offset 0,4-4294967292
BUF_SIZE 0 ring 13600
BUF_SIZE 0 ring 13600
DATA_SOURCE 0 ring $0
BIT_INFO 2 reg_offset 0x0,0xfffffffc
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->wptr 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &vinst->vcn_pg_lock

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c jpeg_v1_0_decode_ring_set_patch_ring() -> jpeg_v1_0_decode_ring_patch_wreg()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 ring->ring 4096-ptr_max
PARAM_VALUE 1 ptr 4096-ptr_max
PARAM_VALUE 2 reg_offset 0,4-4294967292
PARAM_VALUE 3 val 19
BUF_SIZE 0 ring 13600
BUF_SIZE 0 ring 13600
DATA_SOURCE 0 ring $0
BIT_INFO 2 reg_offset 0x0,0xfffffffc
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->wptr 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &vinst->vcn_pg_lock

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c jpeg_v1_0_decode_ring_set_patch_ring() -> jpeg_v1_0_decode_ring_patch_wreg()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 ring->ring 4096-ptr_max
PARAM_VALUE 1 ptr 4096-ptr_max
PARAM_VALUE 2 reg_offset 0,4-4294967292
PARAM_VALUE 3 val 1
BUF_SIZE 0 ring 13600
BUF_SIZE 0 ring 13600
DATA_SOURCE 0 ring $0
BIT_INFO 2 reg_offset 0x0,0xfffffffc
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->wptr 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &vinst->vcn_pg_lock

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c jpeg_v1_0_decode_ring_set_patch_ring() -> jpeg_v1_0_decode_ring_patch_wreg()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 ring->ring 4096-ptr_max
PARAM_VALUE 1 ptr 4096-ptr_max
PARAM_VALUE 2 reg_offset 0,4-4294967292
PARAM_VALUE 3 val 0
BUF_SIZE 0 ring 13600
BUF_SIZE 0 ring 13600
DATA_SOURCE 0 ring $0
BIT_INFO 2 reg_offset 0x0,0xfffffffc
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->wptr 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &vinst->vcn_pg_lock

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c jpeg_v1_0_decode_ring_set_patch_ring() -> jpeg_v1_0_decode_ring_patch_wreg()

Type Parameter Key Value
PARAM_VALUE 0 ring 4096-ptr_max
PARAM_VALUE 0 ring->adev 4096-ptr_max
PARAM_VALUE 0 ring->adev->reg_offset 4096-ptr_max
PARAM_VALUE 0 ring->ring 4096-ptr_max
PARAM_VALUE 1 ptr 4096-ptr_max
PARAM_VALUE 2 reg_offset 0,4-4294967292
PARAM_VALUE 3 val 18
BUF_SIZE 0 ring 13600
BUF_SIZE 0 ring 13600
DATA_SOURCE 0 ring $0
BIT_INFO 2 reg_offset 0x0,0xfffffffc
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 ring->wptr 0-u32max
HALF_LOCKED2 &adev->reset_domain->sem
HALF_LOCKED2 &vinst->vcn_pg_lock