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Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

kernel/irq/irqdomain.c irq_domain_activate_irq() -> irqd_set_activated()

Type Parameter Key Value
PARAM_VALUE 0 d 4096-ptr_max
BUF_SIZE 0 d (-1),56
BUF_SIZE 0 d (-1),56
DATA_SOURCE 0 d $0
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 d->chip_data->iommu->acpi_flags 0-255
HOST_DATA 0 d->chip_data->iommu->cap 0-4294967295
HOST_DATA 0 d->chip_data->iommu->cap_ptr 0-u16max
HOST_DATA 0 d->chip_data->iommu->cmd_buf_head 0-4294967295
HOST_DATA 0 d->chip_data->iommu->cmd_buf_tail 0-8191
HOST_DATA 0 d->chip_data->iommu->cmd_sem_paddr s64min-s64max
HOST_DATA 0 d->chip_data->iommu->cmd_sem_val s64min-s64max
HOST_DATA 0 d->chip_data->iommu->dbg_cap_offset s32min-s32max
HOST_DATA 0 d->chip_data->iommu->dbg_mmio_offset s32min-s32max
HOST_DATA 0 d->chip_data->iommu->devid 0-u16max
HOST_DATA 0 d->chip_data->iommu->features s64min-s64max
HOST_DATA 0 d->chip_data->iommu->features2 s64min-s64max
HOST_DATA 0 d->chip_data->iommu->flags 0-4294967295
HOST_DATA 0 d->chip_data->iommu->index s32min-s32max
HOST_DATA 0 d->chip_data->iommu->int_enabled 0-1
HOST_DATA 0 d->chip_data->iommu->iommu.max_pasids 0-4294967295
HOST_DATA 0 d->chip_data->iommu->iommu.ready 0-1
HOST_DATA 0 d->chip_data->iommu->irtcachedis_enabled 0-1
HOST_DATA 0 d->chip_data->iommu->max_banks 0-255
HOST_DATA 0 d->chip_data->iommu->max_counters 0-255
HOST_DATA 0 d->chip_data->iommu->mmio_phys s64min-s64max
HOST_DATA 0 d->chip_data->iommu->mmio_phys_end s64min-s64max
HOST_DATA 0 d->chip_data->iommu->need_sync 1
HOST_DATA 0 d->chip_data->iommu->stored_addr_hi 0-4294967295
HOST_DATA 0 d->chip_data->iommu->stored_addr_lo 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->acpi_flags 0-255
HOST_DATA 0 d->parent_data->chip_data->iommu->cap 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->cap_ptr 0-u16max
HOST_DATA 0 d->parent_data->chip_data->iommu->cmd_buf_head 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->cmd_buf_tail 0-8191
HOST_DATA 0 d->parent_data->chip_data->iommu->cmd_sem_paddr s64min-s64max
HOST_DATA 0 d->parent_data->chip_data->iommu->cmd_sem_val s64min-s64max
HOST_DATA 0 d->parent_data->chip_data->iommu->dbg_cap_offset s32min-s32max
HOST_DATA 0 d->parent_data->chip_data->iommu->dbg_mmio_offset s32min-s32max
HOST_DATA 0 d->parent_data->chip_data->iommu->devid 0-u16max
HOST_DATA 0 d->parent_data->chip_data->iommu->features s64min-s64max
HOST_DATA 0 d->parent_data->chip_data->iommu->features2 s64min-s64max
HOST_DATA 0 d->parent_data->chip_data->iommu->flags 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->index s32min-s32max
HOST_DATA 0 d->parent_data->chip_data->iommu->int_enabled 0-1
HOST_DATA 0 d->parent_data->chip_data->iommu->iommu.max_pasids 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->iommu.ready 0-1
HOST_DATA 0 d->parent_data->chip_data->iommu->irtcachedis_enabled 0-1
HOST_DATA 0 d->parent_data->chip_data->iommu->lock.magic 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->lock.raw_lock.locked 0-255
HOST_DATA 0 d->parent_data->chip_data->iommu->lock.raw_lock.locked_pending 0-u16max
HOST_DATA 0 d->parent_data->chip_data->iommu->lock.raw_lock.pending 0-255
HOST_DATA 0 d->parent_data->chip_data->iommu->lock.raw_lock.tail 0-u16max
HOST_DATA 0 d->parent_data->chip_data->iommu->lock.raw_lock.val.counter s32min-s32max
HOST_DATA 0 d->parent_data->chip_data->iommu->max_banks 0-255
HOST_DATA 0 d->parent_data->chip_data->iommu->max_counters 0-255
HOST_DATA 0 d->parent_data->chip_data->iommu->mmio_phys s64min-s64max
HOST_DATA 0 d->parent_data->chip_data->iommu->mmio_phys_end s64min-s64max
HOST_DATA 0 d->parent_data->chip_data->iommu->need_sync 1
HOST_DATA 0 d->parent_data->chip_data->iommu->stored_addr_hi 0-4294967295
HOST_DATA 0 d->parent_data->chip_data->iommu->stored_addr_lo 0-4294967295
HOST_DATA 0 *d->chip_data->iommu s64min-s64max
HOST_DATA 0 *d->parent_data->chip_data->iommu s64min-s64max
HALF_LOCKED2 &_T->lock->msi.data->mutex
HALF_LOCKED2 irq