Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 2 files:
Smatch caller information:
drivers/gpu/drm/i915/display/intel_dpll_mgr.c dg2_compute_dplls() -> intel_mpllb_calc_port_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 1 | pll_state | 4096-ptr_max |
| DATA_SOURCE | 0 | encoder | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_dpll_mgr.c dg2_mpllb_get_freq() -> intel_mpllb_calc_port_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->type | 6-8,10 |
| PARAM_VALUE | 1 | pll_state | 4096-ptr_max |
| DATA_SOURCE | 0 | encoder | r dg2_get_intel_encoder |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_ddi.c dg2_ddi_get_config() -> intel_mpllb_calc_port_clock()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->base.funcs->debugfs_init | 0,6973352036378669056 |
| PARAM_VALUE | 0 | encoder->base.funcs->destroy | 0,4096-ptr_max |
| PARAM_VALUE | 0 | encoder->base.funcs->early_unregister | 0,4760937263027425280 |
| PARAM_VALUE | 0 | encoder->base.funcs->late_register | 0,701314789818085376,1181227410646614016,1647545275053064192,2341737043894939648,3940292699586646016,6122176978846912512 |
| PARAM_VALUE | 0 | encoder->base.funcs->reset | 0,4096-ptr_max |
| PARAM_VALUE | 1 | pll_state | 4096-ptr_max |
| PARAM_VALUE | 1 | pll_state->mpllb_div | 0-s32max |
| PARAM_VALUE | 1 | pll_state->ref_control | 0,134217728-u32max |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder->base.crtc | (-1),2048 |
| DATA_SOURCE | 0 | encoder | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 1 | pll_state->mpllb_cp | 0-u32max |
| HOST_DATA | 1 | pll_state->mpllb_div | 0-s32max[c] |
| HOST_DATA | 1 | pll_state->mpllb_div2 | 0-u32max |
| HOST_DATA | 1 | pll_state->mpllb_fracn1 | 0-u32max |
| HOST_DATA | 1 | pll_state->mpllb_fracn2 | 0-u32max |
| HOST_DATA | 1 | pll_state->mpllb_sscen | 0-u32max |
| HOST_DATA | 1 | pll_state->mpllb_sscstep | 0-u32max |
| HOST_DATA | 1 | pll_state->ref_control | 0,134217728-u32max |
| NO_OVERFLOW_SIMPLE | 0 | encoder->base.dev->num_crtcs |