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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 1
PARAM_VALUE 2 addr 1034
PARAM_VALUE 3 data 1
PARAM_VALUE 5 expected_mac_val 1
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 1
PARAM_VALUE 2 addr 1034
PARAM_VALUE 3 data 0
PARAM_VALUE 5 expected_mac_val 0
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 1
PARAM_VALUE 2 addr 1546
PARAM_VALUE 3 data 1
PARAM_VALUE 5 expected_mac_val 1
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 1
PARAM_VALUE 2 addr 1546
PARAM_VALUE 3 data 0
PARAM_VALUE 5 expected_mac_val 0
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 2
PARAM_VALUE 2 addr 1034
PARAM_VALUE 3 data 1
PARAM_VALUE 5 expected_mac_val 1
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 2
PARAM_VALUE 2 addr 1034
PARAM_VALUE 3 data 0
PARAM_VALUE 5 expected_mac_val 0
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 2
PARAM_VALUE 2 addr 1546
PARAM_VALUE 3 data 1
PARAM_VALUE 5 expected_mac_val 1
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_enable_disable_tx() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 2
PARAM_VALUE 2 addr 1546
PARAM_VALUE 3 data 0
PARAM_VALUE 5 expected_mac_val 0
DATA_SOURCE 0 encoder $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock

drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_pll_enable() -> intel_lt_phy_p2p_write()

Type Parameter Key Value
PARAM_VALUE 0 encoder 4096-ptr_max
PARAM_VALUE 1 lane_mask 1,3
PARAM_VALUE 2 addr 3268
PARAM_VALUE 3 data 1
PARAM_VALUE 5 expected_mac_val 1
DATA_SOURCE 0 encoder $0
DATA_SOURCE 1 lane_mask r intel_lt_phy_get_owned_lane_mask
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &display->dpll.lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct intel_dpll_global)->lock