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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_display.c intel_atomic_check() -> intel_joiner_adjust_pipe_src()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state r intel_atomic_get_new_crtc_state
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_src_size() -> intel_joiner_adjust_pipe_src()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
PARAM_VALUE 0 crtc_state->output_format 0,2
PARAM_VALUE 0 crtc_state->pipe_bpp 0,18,24,30,36
PARAM_VALUE 0 crtc_state->pipe_src.x1 0
PARAM_VALUE 0 crtc_state->pipe_src.x2 0-s32max
PARAM_VALUE 0 crtc_state->pipe_src.y1 0
PARAM_VALUE 0 crtc_state->pipe_src.y2 0-s32max
PARAM_VALUE 0 crtc_state->sink_format 0,2
PARAM_VALUE 0 crtc_state->uapi.crtc 4096-ptr_max
DATA_SOURCE 0 crtc_state $1
FUZZY_MAX 0 crtc_state->output_format 2
FUZZY_MAX 0 crtc_state->pipe_bpp 36
BIT_INFO 0 crtc_state->output_format 0x0,0x2
BIT_INFO 0 crtc_state->pipe_bpp 0x0,0x3e
BIT_INFO 0 crtc_state->sink_format 0x0,0x2
HARD_MAX 0 crtc_state->output_format 2
HARD_MAX 0 crtc_state->pipe_bpp 36
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 crtc_state->cgm_mode 0-u32max
HOST_DATA 0 crtc_state->csc_mode 0-u32max
HOST_DATA 0 crtc_state->double_wide 0-1
HOST_DATA 0 crtc_state->dsc.config.block_pred_enable 0-1
HOST_DATA 0 crtc_state->dsc.config.convert_rgb 0-1
HOST_DATA 0 crtc_state->dsc.config.native_422 0-1
HOST_DATA 0 crtc_state->dsc.config.simple_422 0-1
HOST_DATA 0 crtc_state->dsc.config.vbr_enable 0-1
HOST_DATA 0 crtc_state->fdi_m_n.data_m 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.data_n 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.link_m 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.link_n 0-16777215
HOST_DATA 0 crtc_state->gamma_mode 0-u32max
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_clock 0-s32max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_vtotal 0-u16max
HOST_DATA 0 crtc_state->hw.background_color 0-1073741823
HOST_DATA 0 crtc_state->min_hblank 0-s32max
HOST_DATA 0 crtc_state->msa_timing_delay 0-255[c]
HOST_DATA 0 crtc_state->set_context_latency 0-u16max
HOST_DATA 0 crtc_state->vrr.cmrr.cmrr_m 0-u64max
HOST_DATA 0 crtc_state->vrr.cmrr.cmrr_n 0-u64max
HOST_DATA 0 crtc_state->vrr.dc_balance.guardband 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.max_decrease 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.max_increase 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.slope 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.vblank_target 0-u16max
HOST_DATA 0 crtc_state->vrr.flipline 0-u16max
HOST_DATA 0 crtc_state->vrr.guardband 0-u16max[c]
HOST_DATA 0 crtc_state->vrr.pipeline_full 0-255[c]
HOST_DATA 0 crtc_state->vrr.vmax 0-u16max
HOST_DATA 0 crtc_state->vrr.vmin 0-u16max
HOST_DATA 0 crtc_state->vrr.vsync_end 0-u32max[c]
HOST_DATA 0 crtc_state->vrr.vsync_start 0-u32max[c]
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->num_crtcs
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->num_crtcs