Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 3 files:
- drivers/gpu/drm/i915/display/intel_dp_tunnel.c, line 783
- drivers/gpu/drm/i915/display/intel_dpll.c
- drivers/gpu/drm/i915/display/intel_pch_display.c, line 436
Smatch caller information:
drivers/gpu/drm/i915/display/intel_dpll.c hsw_crtc_compute_clock() -> intel_get_crtc_new_encoder()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | state | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.acquire_ctx->locked.next->next | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.acquire_ctx->locked.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.crtcs | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.dev | 4096-ptr_max |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_crtc | 1 |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_total_plane | 1 |
| DATA_SOURCE | 0 | state | $0 |
| DATA_SOURCE | 1 | crtc_state | r intel_atomic_get_new_crtc_state |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_dpll.c hsw_crtc_get_dpll() -> intel_get_crtc_new_encoder()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | state | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.acquire_ctx->locked.next->next | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.acquire_ctx->locked.next->prev | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.crtcs | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.dev | 4096-ptr_max |
| PARAM_VALUE | 0 | state->hw.ctm*state)->base.dev->mode_config.object_idr.idr_rt.xa_head | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | state->hw.ctm->base.base.id | 0 |
| PARAM_VALUE | 0 | state->hw.ctm->base.dev->mode_config.blob_lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | state->hw.ctm->base.dev->mode_config.idr_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | state->hw.ctm->base.dev->mode_config.idr_mutex.first_waiter->list.prev->prev | 5159360019465732096 |
| PARAM_VALUE | 0 | state->hw.ctm->base.dev->mode_config.object_idr.idr_rt.xa_flags | 0-4294967295 |
| PARAM_VALUE | 0 | state->hw.degamma_lut*state)->base.dev->mode_config.object_idr.idr_rt.xa_head | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | state->hw.degamma_lut->base.base.id | 0 |
| PARAM_VALUE | 0 | state->hw.degamma_lut->base.dev->mode_config.blob_lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | state->hw.degamma_lut->base.dev->mode_config.object_idr.idr_rt.xa_flags | 0-4294967295 |
| PARAM_VALUE | 0 | state->hw.gamma_lut*state)->base.dev->mode_config.object_idr.idr_rt.xa_head | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | state->hw.gamma_lut->base.base.id | 0 |
| PARAM_VALUE | 0 | state->hw.gamma_lut->base.dev->mode_config.blob_lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | state->hw.gamma_lut->base.dev->mode_config.idr_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | state->hw.gamma_lut->base.dev->mode_config.idr_mutex.first_waiter->list.prev->prev | 5159360019465732096 |
| PARAM_VALUE | 0 | state->hw.gamma_lut->base.dev->mode_config.object_idr.idr_rt.xa_flags | 0-4294967295 |
| PARAM_VALUE | 0 | state->hw.lut_3d*state)->base.dev->mode_config.object_idr.idr_rt.xa_head | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | state->hw.lut_3d->base.base.id | 0 |
| PARAM_VALUE | 0 | state->hw.lut_3d->base.dev->mode_config.blob_lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | state->hw.lut_3d->base.dev->mode_config.idr_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | state->hw.lut_3d->base.dev->mode_config.idr_mutex.first_waiter->list.prev->prev | 5159360019465732096 |
| PARAM_VALUE | 0 | state->hw.lut_3d->base.dev->mode_config.object_idr.idr_rt.xa_flags | 0-4294967295 |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_crtc | 1 |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_total_plane | 1 |
| DATA_SOURCE | 0 | state | $0 |
| DATA_SOURCE | 1 | crtc_state | r intel_atomic_get_new_crtc_state |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_dp_tunnel.c queue_retry_work() -> intel_get_crtc_new_encoder()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | state | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.crtcs | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.dev | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->dp_tunnel_ref.tunnel | 4096-ptr_max |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_crtc | 1 |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_total_plane | 1 |
| CAPPED_DATA | 0 | state->base.num_connector | 1 |
| CAPPED_DATA | 0 | state->base.num_private_objs | 1 |
| DATA_SOURCE | 0 | state | $0 |
| DATA_SOURCE | 1 | crtc_state | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &pool->lock |
drivers/gpu/drm/i915/display/intel_pch_display.c ilk_pch_enable() -> intel_get_crtc_new_encoder()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | state | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.crtcs | 4096-ptr_max |
| PARAM_VALUE | 0 | state->base.dev | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->intel_dpll | 0,4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->intel_dpll->info->id | 0-8 |
| PARAM_VALUE | 1 | crtc_state->intel_dpll->info->power_domain | 0,73 |
| PARAM_VALUE | 1 | crtc_state->intel_dpll->on | 1 |
| PARAM_VALUE | 1 | crtc_state->intel_dpll->wakeref | 4096-ptr_max,(-2) |
| PARAM_VALUE | 1 | crtc_state->output_types | 128-u32max |
| PARAM_VALUE | 1 | crtc_state->uapi.crtc | 4096-ptr_max |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_crtc | 1 |
| CAPPED_DATA | 0 | state->base.dev->mode_config.num_total_plane | 1 |
| CAPPED_DATA | 0 | state->base.num_connector | 1 |
| CAPPED_DATA | 0 | state->base.num_private_objs | 1 |
| CAPPED_DATA | 0 | state->num_global_objs | 1 |
| DATA_SOURCE | 0 | state | $0 |
| DATA_SOURCE | 1 | crtc_state | r intel_atomic_get_new_crtc_state |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &pool->lock |