Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 4 files:
- drivers/gpu/drm/i915/display/intel_dp.c, line 2354
- drivers/gpu/drm/i915/display/intel_dp_mst.c, line 887
- drivers/gpu/drm/i915/display/intel_link_bw.c, line 69
- drivers/gpu/drm/i915/display/intel_psr.c
Smatch caller information:
drivers/gpu/drm/i915/display/intel_dp.c intel_dp_needs_8b10b_fec() -> intel_dsc_enabled_on_link()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 0 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 0 | crtc_state->port_clock | s32min-999999 |
| PARAM_VALUE | 0 | crtc_state->sink_format | 0-1 |
| CAPPED_DATA | 0 | crtc_state->sink_format | 1 |
| DATA_SOURCE | 0 | crtc_state | $0 |
| HARD_MAX | 0 | crtc_state->port_clock | 999999 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | crtc_state->hw.adjusted_mode.crtc_clock |
drivers/gpu/drm/i915/display/intel_link_bw.c intel_link_bw_init_limits() -> intel_dsc_enabled_on_link()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| DATA_SOURCE | 0 | crtc_state | r intel_atomic_get_new_crtc_state |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp_mst_check_dsc_change() -> intel_dsc_enabled_on_link()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 1-u64max |
| DATA_SOURCE | 0 | crtc_state | r intel_atomic_get_new_crtc_state |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_psr.c _panel_replay_compute_config() -> intel_dsc_enabled_on_link()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->crc_enabled | 0 |
| PARAM_VALUE | 0 | crtc_state->framestart_delay | 1 |
| PARAM_VALUE | 0 | crtc_state->joiner_pipes | 0 |
| PARAM_VALUE | 0 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 0 | crtc_state->pipe_src.x1 | 0 |
| PARAM_VALUE | 0 | crtc_state->pipe_src.x2 | 0-u16max |
| PARAM_VALUE | 0 | crtc_state->pipe_src.y1 | 0 |
| PARAM_VALUE | 0 | crtc_state->pipe_src.y2 | 0-u16max |
| PARAM_VALUE | 0 | crtc_state->pixel_multiplier | 1 |
| PARAM_VALUE | 0 | crtc_state->sink_format | 0-1 |
| PARAM_VALUE | 0 | crtc_state->uapi.crtc | 4096-ptr_max |
| PARAM_VALUE | 0 | *crtc_state->eld | 0-255 |
| DATA_SOURCE | 0 | crtc_state | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | crtc_state->hw.adjusted_mode.crtc_clock |
drivers/gpu/drm/i915/display/intel_psr.c intel_sel_update_config_valid() -> intel_dsc_enabled_on_link()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->framestart_delay | 1 |
| PARAM_VALUE | 0 | crtc_state->has_panel_replay | 1 |
| PARAM_VALUE | 0 | crtc_state->has_psr | 1 |
| PARAM_VALUE | 0 | crtc_state->joiner_pipes | 0 |
| PARAM_VALUE | 0 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 0 | crtc_state->pipe_src.x1 | 0 |
| PARAM_VALUE | 0 | crtc_state->pipe_src.x2 | 0-u16max |
| PARAM_VALUE | 0 | crtc_state->pipe_src.y1 | 0 |
| PARAM_VALUE | 0 | crtc_state->pipe_src.y2 | 0-u16max |
| PARAM_VALUE | 0 | crtc_state->pixel_multiplier | 1 |
| PARAM_VALUE | 0 | crtc_state->sink_format | 0-1 |
| PARAM_VALUE | 0 | crtc_state->uapi.crtc | 4096-ptr_max |
| PARAM_VALUE | 0 | *crtc_state->eld | 0-255 |
| DATA_SOURCE | 0 | crtc_state | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | crtc_state->hw.adjusted_mode.crtc_clock |
drivers/gpu/drm/i915/display/intel_psr.c verify_panel_replay_dsc_state() -> intel_dsc_enabled_on_link()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->has_panel_replay | 1 |
| PARAM_VALUE | 0 | crtc_state->has_psr | 1 |
| PARAM_VALUE | 0 | crtc_state->uapi.crtc | 4096-ptr_max |
| DATA_SOURCE | 0 | crtc_state | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HALF_LOCKED2 | &pool->lock |