Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 2 files:
Smatch caller information:
drivers/gpu/drm/i915/display/intel_dp.c dsc_compute_link_config() -> intel_dp_mtp_tu_compute_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | intel_dp | 4096-ptr_max |
| PARAM_VALUE | 0 | intel_dp->link.caps | 4096-ptr_max |
| PARAM_VALUE | 0 | intel_dp->link.caps->num_configs | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | intel_dp->tunnel->bw_alloc_enabled | 0-1 |
| PARAM_VALUE | 1 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->framestart_delay | 1 |
| PARAM_VALUE | 1 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 1 | crtc_state->pipe_bpp | 0-s32max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pixel_multiplier | 1 |
| PARAM_VALUE | 1 | crtc_state->port_clock | 1000000-s32max |
| PARAM_VALUE | 1 | crtc_state->sink_format | 0-1 |
| PARAM_VALUE | 2 | conn_state | 4096-ptr_max |
| PARAM_VALUE | 2 | conn_state->crtc | 4096-ptr_max |
| PARAM_VALUE | 3 | min_bpp_x16 | 1-s32max |
| PARAM_VALUE | 4 | max_bpp_x16 | 1-s32max |
| PARAM_VALUE | 5 | bpp_step_x16 | 0 |
| PARAM_VALUE | 6 | dsc | 1 |
| CAPPED_DATA | 1 | crtc_state->sink_format | 1 |
| CAPPED_DATA | 2 | conn_state->crtc | 1 |
| CAPPED_DATA | 3 | min_bpp_x16 | 1 |
| CAPPED_DATA | 4 | max_bpp_x16 | 1 |
| DATA_SOURCE | 0 | intel_dp | $0 |
| DATA_SOURCE | 1 | crtc_state | $1 |
| DATA_SOURCE | 2 | conn_state | $2 |
| DATA_SOURCE | 3 | min_bpp_x16 | $4 |
| DATA_SOURCE | 4 | max_bpp_x16 | $4 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 1 | crtc_state->hw.adjusted_mode.crtc_clock |
drivers/gpu/drm/i915/display/intel_dp.c intel_dp_compute_link_for_joined_pipes() -> intel_dp_mtp_tu_compute_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | intel_dp | 4096-ptr_max |
| PARAM_VALUE | 0 | intel_dp->dfp.max_bpc | 0,8,10,12,16 |
| PARAM_VALUE | 0 | intel_dp->dfp.min_tmds_clock | 0,25000 |
| PARAM_VALUE | 0 | intel_dp->force_dsc_en | 0 |
| PARAM_VALUE | 0 | intel_dp->link.caps | 4096-ptr_max |
| PARAM_VALUE | 0 | intel_dp->link.caps->num_configs | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | intel_dp->tunnel | 0,4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->dsc.compressed_bpp_x16 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->fec_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->framestart_delay | 1 |
| PARAM_VALUE | 1 | crtc_state->hw.adjusted_mode.clock | (-2147483647)-s32max |
| PARAM_VALUE | 1 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 1 | crtc_state->pipe_bpp | 0-134217727 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pixel_multiplier | 1 |
| PARAM_VALUE | 1 | crtc_state->port_clock | 1000000-s32max |
| PARAM_VALUE | 1 | crtc_state->sink_format | 0-1 |
| PARAM_VALUE | 2 | conn_state | 4096-ptr_max |
| PARAM_VALUE | 2 | conn_state->crtc | 4096-ptr_max |
| PARAM_VALUE | 3 | min_bpp_x16 | 0,16-2147483632 |
| PARAM_VALUE | 4 | max_bpp_x16 | 0,16-2147483632 |
| PARAM_VALUE | 5 | bpp_step_x16 | 0 |
| PARAM_VALUE | 6 | dsc | 0 |
| BUF_SIZE | 0 | intel_dp | 6896 |
| CAPPED_DATA | 0 | intel_dp->dfp.min_tmds_clock | 1 |
| CAPPED_DATA | 0 | intel_dp->link.caps->forced_params.rate | 1 |
| CAPPED_DATA | 1 | crtc_state->sink_format | 1 |
| CAPPED_DATA | 2 | conn_state->crtc | 1 |
| DATA_SOURCE | 0 | intel_dp | r enc_to_intel_dp |
| DATA_SOURCE | 1 | crtc_state | $1 |
| DATA_SOURCE | 2 | conn_state | $2 |
| BIT_INFO | 3 | min_bpp_x16 | 0x0,0x7fffffff |
| BIT_INFO | 4 | max_bpp_x16 | 0x0,0x7fffffff |
| MEM_ZERO | 1 | &crtc_state->dsc.config | |
| MEM_ZERO | 1 | &crtc_state->dsc.slice_config | |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/i915/display/intel_dp_mst.c mst_stream_compute_link_config() -> intel_dp_mtp_tu_compute_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | intel_dp | 4096-ptr_max |
| PARAM_VALUE | 0 | intel_dp->force_dsc_en | 0 |
| PARAM_VALUE | 1 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->dsc.compressed_bpp_x16 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->fec_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->framestart_delay | 1 |
| PARAM_VALUE | 1 | crtc_state->hw.adjusted_mode.flags | 0,4-u32max |
| PARAM_VALUE | 1 | crtc_state->output_format | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_bpp | 0-s32max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pixel_multiplier | 1 |
| PARAM_VALUE | 1 | crtc_state->sink_format | 0 |
| PARAM_VALUE | 1 | crtc_state->uapi.crtc | 4096-ptr_max |
| PARAM_VALUE | 2 | conn_state | 4096-ptr_max |
| PARAM_VALUE | 2 | conn_state->crtc | 4096-ptr_max |
| PARAM_VALUE | 3 | min_bpp_x16 | 1-s32max |
| PARAM_VALUE | 4 | max_bpp_x16 | 1-s32max |
| PARAM_VALUE | 5 | bpp_step_x16 | 96 |
| PARAM_VALUE | 6 | dsc | 0 |
| BUF_SIZE | 0 | intel_dp | 6896 |
| CAPPED_DATA | 2 | conn_state->crtc | 1 |
| DATA_SOURCE | 0 | intel_dp | $0 |
| DATA_SOURCE | 1 | crtc_state | $1 |
| DATA_SOURCE | 2 | conn_state | $2 |
| MEM_ZERO | 1 | &crtc_state->dsc.config | |
| MEM_ZERO | 1 | &crtc_state->dsc.slice_config | |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 1 | crtc_state->hw.adjusted_mode.crtc_clock |
drivers/gpu/drm/i915/display/intel_dp_mst.c mst_stream_dsc_compute_link_config() -> intel_dp_mtp_tu_compute_config()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | intel_dp | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 1 | crtc_state->dsc.compressed_bpp_x16 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 1 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 1 | crtc_state->framestart_delay | 1 |
| PARAM_VALUE | 1 | crtc_state->hw.adjusted_mode.flags | 0,4-u32max |
| PARAM_VALUE | 1 | crtc_state->output_format | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_bpp | 0-s32max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.x2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y1 | 0 |
| PARAM_VALUE | 1 | crtc_state->pipe_src.y2 | 0-u16max |
| PARAM_VALUE | 1 | crtc_state->pixel_multiplier | 1 |
| PARAM_VALUE | 1 | crtc_state->sink_format | 0 |
| PARAM_VALUE | 1 | crtc_state->uapi.crtc | 4096-ptr_max |
| PARAM_VALUE | 2 | conn_state | 4096-ptr_max |
| PARAM_VALUE | 2 | conn_state->crtc | 4096-ptr_max |
| PARAM_VALUE | 3 | min_bpp_x16 | 1-s32max |
| PARAM_VALUE | 4 | max_bpp_x16 | 1-s32max |
| PARAM_VALUE | 5 | bpp_step_x16 | 1-2,4,8-16 |
| PARAM_VALUE | 6 | dsc | 1 |
| BUF_SIZE | 0 | intel_dp | 6896 |
| CAPPED_DATA | 2 | conn_state->crtc | 1 |
| DATA_SOURCE | 0 | intel_dp | $0 |
| DATA_SOURCE | 1 | crtc_state | $1 |
| DATA_SOURCE | 2 | conn_state | $2 |
| MEM_ZERO | 1 | &crtc_state->dsc.config | |
| MEM_ZERO | 1 | &crtc_state->dsc.slice_config | |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 1 | crtc_state->hw.adjusted_mode.crtc_clock |