Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp_mtp_tu_compute_config() -> intel_dp_mst_bw_overhead()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 0 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 0 | crtc_state->pipe_bpp | 0-s32max |
| PARAM_VALUE | 0 | crtc_state->sink_format | 0-1 |
| PARAM_VALUE | 0 | crtc_state->uapi.crtc | 4096-ptr_max |
| PARAM_VALUE | 1 | ssc | 0 |
| PARAM_VALUE | 2 | dsc_slice_count | 0-255 |
| PARAM_VALUE | 3 | bpp_x16 | s32min-(-16),0-s32max |
| CAPPED_DATA | 0 | crtc_state->sink_format | 1 |
| DATA_SOURCE | 0 | crtc_state | $1 |
| FUZZY_MAX | 2 | dsc_slice_count | 0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | crtc_state->hw.adjusted_mode.crtc_clock |
drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp_mtp_tu_compute_config() -> intel_dp_mst_bw_overhead()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | crtc_state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->dp_m_n.data_m | 0-16777215 |
| PARAM_VALUE | 0 | crtc_state->dp_m_n.data_n | 0-16777215 |
| PARAM_VALUE | 0 | crtc_state->dp_m_n.link_m | 0-16777215 |
| PARAM_VALUE | 0 | crtc_state->dp_m_n.link_n | 0-16777215 |
| PARAM_VALUE | 0 | crtc_state->dsc.compression_enable | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.bits_per_pixel | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.convert_rgb | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.final_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.flatness_max_qp | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.flatness_min_qp | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.initial_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.line_buf_depth | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.mux_word_size | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.native_420 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.native_422 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.nfl_bpg_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.nsl_bpg_offset | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.pic_height | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.pic_width | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_bits | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_edge_factor | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.rc_model_size | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.simple_422 | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_count | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_height | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.slice_width | 0 |
| PARAM_VALUE | 0 | crtc_state->dsc.config.vbr_enable | 0 |
| PARAM_VALUE | 0 | crtc_state->output_format | 0-2 |
| PARAM_VALUE | 0 | crtc_state->pipe_bpp | 0-s32max |
| PARAM_VALUE | 0 | crtc_state->sink_format | 0-1 |
| PARAM_VALUE | 0 | crtc_state->uapi.crtc | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->uapi.state | 4096-ptr_max |
| PARAM_VALUE | 0 | crtc_state->uapi.state->acquire_ctx | 0,4096-ptr_max |
| PARAM_VALUE | 1 | ssc | 1 |
| PARAM_VALUE | 2 | dsc_slice_count | 0-255 |
| PARAM_VALUE | 3 | bpp_x16 | s32min-(-16),0-s32max |
| CAPPED_DATA | 0 | crtc_state->sink_format | 1 |
| DATA_SOURCE | 0 | crtc_state | $1 |
| FUZZY_MAX | 2 | dsc_slice_count | 0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NO_OVERFLOW_SIMPLE | 0 | crtc_state->hw.adjusted_mode.crtc_clock |