Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 2 files:
Smatch caller information:
drivers/gpu/drm/i915/display/intel_lt_phy.c intel_lt_phy_rmw() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1-2 |
| PARAM_VALUE | 2 | addr | 1026-1544 |
| PARAM_VALUE | 3 | clear | 63,248 |
| PARAM_VALUE | 4 | set | 0-248 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| CAPPED_DATA | 2 | addr | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | $1 |
| DATA_SOURCE | 2 | addr | $2 |
| DATA_SOURCE | 3 | clear | $3 |
| DATA_SOURCE | 4 | set | $4 |
| DATA_SOURCE | 5 | committed | $5 |
| FUZZY_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 3 | clear | 248 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c10_msgbus_access_begin() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3184 |
| PARAM_VALUE | 3 | clear | 0 |
| PARAM_VALUE | 4 | set | 4 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c10_msgbus_access_commit() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3184 |
| PARAM_VALUE | 3 | clear | 0 |
| PARAM_VALUE | 4 | set | 1,3 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | $1 |
| FUZZY_MAX | 4 | set | 1 |
| BIT_INFO | 4 | set | 0x1,0x3 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c10_pll_program() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 3 |
| PARAM_VALUE | 2 | addr | 3330 |
| PARAM_VALUE | 3 | clear | 3 |
| PARAM_VALUE | 4 | set | 0-3 |
| PARAM_VALUE | 5 | committed | 1 |
| DATA_SOURCE | 0 | encoder | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &display->dpll.lock |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c20_pll_program() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3328 |
| PARAM_VALUE | 3 | clear | 1 |
| PARAM_VALUE | 4 | set | 0-1 |
| PARAM_VALUE | 5 | committed | 1 |
| DATA_SOURCE | 0 | encoder | $1 |
| DATA_SOURCE | 1 | lane_mask | r intel_cx0_get_owned_lane_mask |
| FUZZY_MAX | 4 | set | 1 |
| HARD_MAX | 4 | set | 1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &display->dpll.lock |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c20_program_vdr_params() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3330 |
| PARAM_VALUE | 3 | clear | 3 |
| PARAM_VALUE | 4 | set | 0-2,4-255 |
| PARAM_VALUE | 5 | committed | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &display->dpll.lock |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c20_program_vdr_params() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3328 |
| PARAM_VALUE | 3 | clear | 222 |
| PARAM_VALUE | 5 | committed | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &display->dpll.lock |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_c20_program_vdr_params() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 3 |
| PARAM_VALUE | 2 | addr | 3329 |
| PARAM_VALUE | 3 | clear | 3 |
| PARAM_VALUE | 4 | set | 0-2,4-255 |
| PARAM_VALUE | 5 | committed | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &display->dpll.lock |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_phy_set_signal_levels() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3107 |
| PARAM_VALUE | 3 | clear | 224 |
| PARAM_VALUE | 4 | set | 0,32-224 |
| PARAM_VALUE | 5 | committed | 0 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | r intel_cx0_get_owned_lane_mask |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_phy_set_signal_levels() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3121 |
| PARAM_VALUE | 3 | clear | 224 |
| PARAM_VALUE | 4 | set | 0,32-224 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | r intel_cx0_get_owned_lane_mask |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_phy_set_signal_levels() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1-2 |
| PARAM_VALUE | 2 | addr | 3456-5488 |
| PARAM_VALUE | 3 | clear | 63 |
| PARAM_VALUE | 4 | set | 0-63 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| CAPPED_DATA | 2 | addr | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| FUZZY_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 1 | lane_mask | 2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_phy_set_signal_levels() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1-2 |
| PARAM_VALUE | 2 | addr | 3457-5489 |
| PARAM_VALUE | 3 | clear | 63 |
| PARAM_VALUE | 4 | set | 0-63 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| CAPPED_DATA | 2 | addr | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| FUZZY_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 1 | lane_mask | 2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_phy_set_signal_levels() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1-2 |
| PARAM_VALUE | 2 | addr | 3458-5490 |
| PARAM_VALUE | 3 | clear | 63 |
| PARAM_VALUE | 4 | set | 0-63 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| CAPPED_DATA | 2 | addr | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| FUZZY_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 1 | lane_mask | 2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_phy_set_signal_levels() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 0 | encoder->get_buf_trans | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1,3 |
| PARAM_VALUE | 2 | addr | 3441 |
| PARAM_VALUE | 3 | clear | 0 |
| PARAM_VALUE | 4 | set | 5 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| BUF_SIZE | 0 | encoder | (-1),728 |
| DATA_SOURCE | 0 | encoder | $0 |
| DATA_SOURCE | 1 | lane_mask | r intel_cx0_get_owned_lane_mask |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_cx0_program_phy_lane() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1-2 |
| PARAM_VALUE | 2 | addr | 1026-1538 |
| PARAM_VALUE | 3 | clear | 64 |
| PARAM_VALUE | 4 | set | 0,64 |
| PARAM_VALUE | 5 | committed | 1 |
| DATA_SOURCE | 0 | encoder | $0 |
| FUZZY_MAX | 1 | lane_mask | 2 |
| FUZZY_MAX | 4 | set | 64 |
| BIT_INFO | 4 | set | 0x0,0x40 |
| HARD_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 4 | set | 64 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &display->dpll.lock |
drivers/gpu/drm/i915/display/intel_cx0_phy.c intel_lnl_mac_transmit_lfps() -> intel_cx0_rmw()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | encoder | 4096-ptr_max |
| PARAM_VALUE | 1 | lane_mask | 1-2 |
| PARAM_VALUE | 2 | addr | 2048-2560 |
| PARAM_VALUE | 3 | clear | 2 |
| PARAM_VALUE | 4 | set | 2 |
| PARAM_VALUE | 5 | committed | 1 |
| BUF_SIZE | 0 | encoder | 728 |
| DATA_SOURCE | 0 | encoder | $0 |
| FUZZY_MAX | 1 | lane_mask | 2 |
| HARD_MAX | 1 | lane_mask | 2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |