intel_crtc_num_joined_pipes identifier - Linux source code next-20260811

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linux

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FIXME
- FIXME
  - next-20260811

Defined in 1 files as a prototype:

drivers/gpu/drm/i915/display/intel_display.h, line 526 (as a prototype)

Defined in 1 files as a function:

drivers/gpu/drm/i915/display/intel_display.c, line 327 (as a function)

Referenced in 5 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_vdsc.c intel_dsc_get_num_vdsc_instances() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
PARAM_VALUE	0	crtc_state->uapi.crtc	4096-ptr_max
DATA_SOURCE	0	crtc_state	$0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA	0	crtc_state->dsc.compression_enable	1

drivers/gpu/drm/i915/display/intel_display_power.c intel_dc3co_port_pipe_compatible() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
DATA_SOURCE	0	crtc_state	$1
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/i915/display/intel_dp.c intel_dp_compute_config_link_bpp_limits() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
CAPPED_DATA	0	crtc_state->sink_format	1
DATA_SOURCE	0	crtc_state	$1
MEM_ZERO	0	&crtc_state->dsc.config
MEM_ZERO	0	&crtc_state->dsc.slice_config
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_dp.c intel_dp_compute_link_for_joined_pipes() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
CAPPED_DATA	0	crtc_state->sink_format	1
DATA_SOURCE	0	crtc_state	$1
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_dp.c intel_dp_compute_min_hblank() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
PARAM_VALUE	0	crtc_state->uapi.crtc	4096-ptr_max
DATA_SOURCE	0	crtc_state	$0
MEM_ZERO	0	&crtc_state->dsc.config
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE	0	crtc_state->hw.adjusted_mode.crtc_clock

drivers/gpu/drm/i915/display/intel_dp.c intel_dp_dsc_compute_config() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
CAPPED_DATA	0	crtc_state->sink_format	1
DATA_SOURCE	0	crtc_state	$1
MEM_ZERO	0	&crtc_state->dsc.config
MEM_ZERO	0	&crtc_state->dsc.slice_config
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE	0	crtc_state->hw.adjusted_mode.crtc_clock

drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp_mst_dsc_get_slice_count() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
PARAM_VALUE	0	crtc_state->uapi.crtc	4096-ptr_max
CAPPED_DATA	0	crtc_state->sink_format	1
DATA_SOURCE	0	crtc_state	$1
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE	0	crtc_state->hw.adjusted_mode.crtc_clock

drivers/gpu/drm/i915/display/intel_display.c intel_crtc_is_ultrajoiner() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
PARAM_VALUE	0	crtc_state->joiner_pipes	1-255
PARAM_VALUE	0	crtc_state->uapi.crtc	4096-ptr_max
CAPPED_DATA	0	crtc_state->dsc.slice_config.streams_per_pipe	1
DATA_SOURCE	0	crtc_state	$0
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2		&pool->lock

drivers/gpu/drm/i915/display/intel_display.c intel_crtc_readout_derived_state() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
BUF_SIZE	0	crtc_state	(-1),4816
BUF_SIZE	0	crtc_state	(-1),4816
DATA_SOURCE	0	crtc_state	$0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA	0	crtc_state->cgm_mode	0-u32max
HOST_DATA	0	crtc_state->csc_mode	0-u32max
HOST_DATA	0	crtc_state->dsc.config.block_pred_enable	0-1
HOST_DATA	0	crtc_state->dsc.config.convert_rgb	0-1
HOST_DATA	0	crtc_state->dsc.config.native_422	0-1
HOST_DATA	0	crtc_state->dsc.config.simple_422	0-1
HOST_DATA	0	crtc_state->dsc.config.vbr_enable	0-1
HOST_DATA	0	crtc_state->fdi_m_n.link_n	0-16777215
HOST_DATA	0	crtc_state->gamma_mode	0-u32max
HOST_DATA	0	crtc_state->gmch_pfit.pgm_ratios	0-u32max
HOST_DATA	0	crtc_state->hw.adjusted_mode.clock	0[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->hw.background_color	0-1073741823
HOST_DATA	0	crtc_state->hw.mode.clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->hw.pipe_mode.clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->ips_enabled	0-1
HOST_DATA	0	crtc_state->min_hblank	0-s32max
HOST_DATA	0	crtc_state->pixel_rate	0-u32max[c]
HOST_DATA	0	crtc_state->set_context_latency	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.guardband	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.max_decrease	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.max_increase	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.slope	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.vblank_target	0-u16max
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->num_crtcs
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->num_crtcs

drivers/gpu/drm/i915/display/intel_display.c intel_joiner_adjust_pipe_src() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
DATA_SOURCE	0	crtc_state	$0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA	0	crtc_state->cgm_mode	0-u32max
HOST_DATA	0	crtc_state->csc_mode	0-u32max
HOST_DATA	0	crtc_state->double_wide	0-1
HOST_DATA	0	crtc_state->dsc.config.block_pred_enable	0-1
HOST_DATA	0	crtc_state->dsc.config.convert_rgb	0-1
HOST_DATA	0	crtc_state->dsc.config.native_422	0-1
HOST_DATA	0	crtc_state->dsc.config.simple_422	0-1
HOST_DATA	0	crtc_state->dsc.config.vbr_enable	0-1
HOST_DATA	0	crtc_state->fdi_m_n.data_m	0-16777215
HOST_DATA	0	crtc_state->fdi_m_n.data_n	0-16777215
HOST_DATA	0	crtc_state->fdi_m_n.link_m	0-16777215
HOST_DATA	0	crtc_state->fdi_m_n.link_n	0-16777215
HOST_DATA	0	crtc_state->gamma_mode	0-u32max
HOST_DATA	0	crtc_state->hw.adjusted_mode.crtc_clock	0-s32max[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->hw.adjusted_mode.crtc_vtotal	0-u16max
HOST_DATA	0	crtc_state->hw.background_color	0-1073741823
HOST_DATA	0	crtc_state->min_hblank	0-s32max
HOST_DATA	0	crtc_state->msa_timing_delay	0-255[c]
HOST_DATA	0	crtc_state->set_context_latency	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.guardband	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.max_decrease	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.max_increase	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.slope	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.vblank_target	0-u16max
HOST_DATA	0	crtc_state->vrr.flipline	0-u16max
HOST_DATA	0	crtc_state->vrr.guardband	0-u16max[c]
HOST_DATA	0	crtc_state->vrr.pipeline_full	0-255[c]
HOST_DATA	0	crtc_state->vrr.vmax	0-u16max
HOST_DATA	0	crtc_state->vrr.vmin	0-u16max
HOST_DATA	0	crtc_state->vrr.vsync_end	0-u32max[c]
HOST_DATA	0	crtc_state->vrr.vsync_start	0-u32max[c]
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->num_crtcs
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->num_crtcs

drivers/gpu/drm/i915/display/intel_display.c intel_joiner_adjust_timings() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
DATA_SOURCE	0	crtc_state	$0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA	0	crtc_state->cgm_mode	0-u32max
HOST_DATA	0	crtc_state->csc_mode	0-u32max
HOST_DATA	0	crtc_state->dsc.config.block_pred_enable	0-1
HOST_DATA	0	crtc_state->dsc.config.convert_rgb	0-1
HOST_DATA	0	crtc_state->dsc.config.native_422	0-1
HOST_DATA	0	crtc_state->dsc.config.simple_422	0-1
HOST_DATA	0	crtc_state->dsc.config.vbr_enable	0-1
HOST_DATA	0	crtc_state->fdi_m_n.link_n	0-16777215
HOST_DATA	0	crtc_state->gamma_mode	0-u32max
HOST_DATA	0	crtc_state->gmch_pfit.pgm_ratios	0-u32max
HOST_DATA	0	crtc_state->hw.adjusted_mode.clock	0[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.crtc_clock	0-s32max[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->hw.adjusted_mode.hdisplay	0[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.hsync_end	0[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.hsync_start	0[c]
HOST_DATA	0	crtc_state->hw.adjusted_mode.htotal	0[c]
HOST_DATA	0	crtc_state->hw.background_color	0-1073741823
HOST_DATA	0	crtc_state->hw.mode.clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_hblank_end	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_hblank_start	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_hdisplay	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_hsync_end	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_hsync_start	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_htotal	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->hw.mode.hsync_end	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.hsync_start	0-u16max[c]
HOST_DATA	0	crtc_state->hw.mode.htotal	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_clock	s32min-s32max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_hblank_end	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_hblank_start	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_hdisplay	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_hsync_end	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_hsync_start	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_htotal	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.crtc_vblank_start	0-u16max
HOST_DATA	0	crtc_state->hw.pipe_mode.hdisplay	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.hsync_end	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.hsync_start	0-u16max[c]
HOST_DATA	0	crtc_state->hw.pipe_mode.htotal	0-u16max[c]
HOST_DATA	0	crtc_state->ips_enabled	0-1
HOST_DATA	0	crtc_state->min_hblank	0-s32max
HOST_DATA	0	crtc_state->pixel_rate	0-u32max[c]
HOST_DATA	0	crtc_state->set_context_latency	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.guardband	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.max_decrease	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.max_increase	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.slope	0-u16max
HOST_DATA	0	crtc_state->vrr.dc_balance.vblank_target	0-u16max
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE	0	crtc_state->post_csc_lut->dev->num_crtcs
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE	0	crtc_state->pre_csc_lut->dev->num_crtcs

drivers/gpu/drm/i915/display/intel_display.c intel_joiner_compute_pipe_src() -> intel_crtc_num_joined_pipes()

Type	Parameter	Key	Value
PARAM_VALUE	0	crtc_state	4096-ptr_max
PARAM_VALUE	0	crtc_state->uapi.crtc	4096-ptr_max
DATA_SOURCE	0	crtc_state	$0
RX_PATH
TASK_NOT_RUNNING