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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 4 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_plane.c intel_add_affected_planes() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 1-u64max
DATA_SOURCE 0 crtc_state r intel_atomic_get_new_crtc_state
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_dpll_disable() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
PARAM_VALUE 0 crtc_state->uapi.crtc 4096-ptr_max
DATA_SOURCE 0 crtc_state $0
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_dpll_enable() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
PARAM_VALUE 0 crtc_state->uapi.crtc 4096-ptr_max
DATA_SOURCE 0 crtc_state $0
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_update_active_dpll() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
DATA_SOURCE 0 crtc_state r intel_atomic_get_new_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &dig_port->tc->lock

drivers/gpu/drm/i915/display/intel_display.c intel_commit_modeset_disables() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state r intel_atomic_get_old_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_display.c intel_commit_modeset_disables() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state r intel_atomic_get_old_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_display.c intel_crtc_num_joined_pipes() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 crtc_state->cgm_mode 0-u32max
HOST_DATA 0 crtc_state->csc_mode 0-u32max
HOST_DATA 0 crtc_state->double_wide 0-1
HOST_DATA 0 crtc_state->dsc.compression_enable 1
HOST_DATA 0 crtc_state->dsc.config.block_pred_enable 0-1
HOST_DATA 0 crtc_state->dsc.config.convert_rgb 0-1
HOST_DATA 0 crtc_state->dsc.config.native_422 0-1
HOST_DATA 0 crtc_state->dsc.config.simple_422 0-1
HOST_DATA 0 crtc_state->dsc.config.vbr_enable 0-1
HOST_DATA 0 crtc_state->fdi_m_n.data_m 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.data_n 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.link_m 0-16777215
HOST_DATA 0 crtc_state->fdi_m_n.link_n 0-16777215
HOST_DATA 0 crtc_state->gamma_mode 0-u32max
HOST_DATA 0 crtc_state->gmch_pfit.pgm_ratios 0-u32max
HOST_DATA 0 crtc_state->hw.adjusted_mode.clock 0[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_clock 0-s32max[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.adjusted_mode.crtc_vtotal 0-u16max
HOST_DATA 0 crtc_state->hw.adjusted_mode.hdisplay 0[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.hsync_end 0[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.hsync_start 0[c]
HOST_DATA 0 crtc_state->hw.adjusted_mode.htotal 0[c]
HOST_DATA 0 crtc_state->hw.background_color 0-1073741823
HOST_DATA 0 crtc_state->hw.mode.clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hblank_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hblank_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.mode.hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.mode.htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_clock s32min-s32max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hblank_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hblank_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_htotal 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.crtc_vblank_start 0-u16max
HOST_DATA 0 crtc_state->hw.pipe_mode.hdisplay 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.hsync_end 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.hsync_start 0-u16max[c]
HOST_DATA 0 crtc_state->hw.pipe_mode.htotal 0-u16max[c]
HOST_DATA 0 crtc_state->ips_enabled 0-1
HOST_DATA 0 crtc_state->min_hblank 0-s32max
HOST_DATA 0 crtc_state->msa_timing_delay 0-255[c]
HOST_DATA 0 crtc_state->pixel_rate 0-u32max[c]
HOST_DATA 0 crtc_state->set_context_latency 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.guardband 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.max_decrease 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.max_increase 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.slope 0-u16max
HOST_DATA 0 crtc_state->vrr.dc_balance.vblank_target 0-u16max
HOST_DATA 0 crtc_state->vrr.flipline 0-u16max
HOST_DATA 0 crtc_state->vrr.guardband 0-u16max[c]
HOST_DATA 0 crtc_state->vrr.pipeline_full 0-255[c]
HOST_DATA 0 crtc_state->vrr.vmax 0-u16max
HOST_DATA 0 crtc_state->vrr.vmin 0-u16max
HOST_DATA 0 crtc_state->vrr.vsync_end 0-u32max[c]
HOST_DATA 0 crtc_state->vrr.vsync_start 0-u32max[c]
NO_OVERFLOW_SIMPLE 0 crtc_state->clock
NO_OVERFLOW_SIMPLE 0 crtc_state->hw.adjusted_mode.crtc_clock
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE 0 crtc_state->post_csc_lut->dev->num_crtcs
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->mode_config.num_colorop
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->mode_config.num_crtc
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->mode_config.num_total_plane
NO_OVERFLOW_SIMPLE 0 crtc_state->pre_csc_lut->dev->num_crtcs

drivers/gpu/drm/i915/display/intel_display.c intel_enable_crtc() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state r intel_atomic_get_new_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_display.c intel_old_crtc_state_disables() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
DATA_SOURCE 0 crtc_state r intel_atomic_get_old_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_display.c intel_old_crtc_state_disables() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
DATA_SOURCE 0 crtc_state r intel_atomic_get_old_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_display.c skl_commit_modeset_enables() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
CAPPED_DATA 0 crtc_state->mst_master_transcoder 1
DATA_SOURCE 0 crtc_state r intel_atomic_get_new_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock

drivers/gpu/drm/i915/display/intel_display.c skl_commit_modeset_enables() -> intel_crtc_joined_pipe_mask()

Type Parameter Key Value
PARAM_VALUE 0 crtc_state 4096-ptr_max
DATA_SOURCE 0 crtc_state r intel_atomic_get_new_crtc_state
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &pool->lock