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Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_cdclk.c _intel_cdclk_prefill_adj() -> intel_cdclk_ppc()

Type Parameter Key Value
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_cdclk.c _intel_pixel_rate_to_cdclk() -> intel_cdclk_ppc()

Type Parameter Key Value
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_cdclk.c intel_cdclk_min_cdclk_for_prefill() -> intel_cdclk_ppc()

Type Parameter Key Value

drivers/gpu/drm/i915/display/intel_cdclk.c intel_compute_max_dotclk() -> intel_cdclk_ppc()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
BUF_SIZE 0 display (-1),8416
BUF_SIZE 0 display (-1),8416
DATA_SOURCE 0 display $0
STR_LEN 0 display (-1),21-22
STR_LEN 0 display (-1),21-22
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 display->cdclk.hw.cdclk 0-39168016[c]
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->cdclk.hw.voltage_level 0-31[c]
HOST_DATA 0 display->cdclk.max_cdclk_freq 0-39168016[c]
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0,4-u32max
HOST_DATA 0 display->fdi.pll_freq 20000-2570000[c]
HOST_DATA 0 display->power.chv_phy_control 0-u32max[c]
HOST_DATA 0 display->power.domains.dc_state 0-1073741835
HOST_DATA 0 display->state.bxt_phy_grc 0-u32max
HOST_DATA 0 display->vbt.lvds_use_ssc 0-1
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
HALF_LOCKED2 0 &display->gmbus.mutex

drivers/gpu/drm/i915/display/intel_modeset_setup.c intel_modeset_readout_hw_state() -> intel_cdclk_ppc()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
BUF_SIZE 0 display (-1),8416
BUF_SIZE 0 display (-1),8416
CAPPED_DATA 0 display->dpll.num_dpll 1
CAPPED_DATA 0 &display->pipe_list 1
DATA_SOURCE 0 display $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 display->cdclk.hw.cdclk 0-39168016[c]
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->cdclk.hw.voltage_level 0-31[c]
HOST_DATA 0 display->cdclk.max_cdclk_freq 1-39168016[c]
HOST_DATA 0 display->dmc.dmc->dc6_allowed.dc5_start 0-4294967295
HOST_DATA 0 display->drm->mode_config.connector_ida.xa.xa_flags 67108869
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0-u32max
HOST_DATA 0 display->drm->mode_config.tile_idr.idr_rt.xa_flags 67108868
HOST_DATA 0 display->drm->num_crtcs 2[c]
HOST_DATA 0 display->fdi.pll_freq 20000-2570000[c]
HOST_DATA 0 display->fdi.rx_config 0,32768-98304[c]
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HOST_DATA 0 display->vbt.lvds_use_ssc 0-1
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
HALF_LOCKED2 0 &display->drm->mode_config.connection_mutex
HALF_LOCKED2 0 &display->drm->mode_config.mutex

drivers/gpu/drm/i915/display/intel_modeset_setup.c intel_modeset_readout_hw_state() -> intel_cdclk_ppc()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
BUF_SIZE 0 display (-1),8416
BUF_SIZE 0 display (-1),8416
CAPPED_DATA 0 display->dpll.num_dpll 1
CAPPED_DATA 0 &display->pipe_list 1
DATA_SOURCE 0 display $0
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 0 display->cdclk.hw.cdclk 0-39168016[c]
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->cdclk.hw.voltage_level 0-31[c]
HOST_DATA 0 display->cdclk.max_cdclk_freq 1-39168016[c]
HOST_DATA 0 display->dmc.dmc->dc6_allowed.dc5_start 0-4294967295
HOST_DATA 0 display->drm->mode_config.connector_ida.xa.xa_flags 67108869
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0-u32max
HOST_DATA 0 display->drm->mode_config.tile_idr.idr_rt.xa_flags 67108868
HOST_DATA 0 display->drm->num_crtcs 2[c]
HOST_DATA 0 display->fdi.pll_freq 20000-2570000[c]
HOST_DATA 0 display->fdi.rx_config 0,32768-98304[c]
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HOST_DATA 0 display->vbt.lvds_use_ssc 0-1
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
HALF_LOCKED2 0 &display->drm->mode_config.connection_mutex
HALF_LOCKED2 0 &display->drm->mode_config.mutex