Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/host1x/hw/host1x05.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 8
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x05.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1-u32max
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x05.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x05.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x05.c synchronize_syncpt_base() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 11
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x10.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x10.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x10.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
HALF_LOCKED2 &ch->cdma.lock
HALF_LOCKED2 &ch->submitlock

drivers/gpu/host1x/hw/host1x10.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
HALF_LOCKED2 &ch->cdma.lock
HALF_LOCKED2 &ch->submitlock

drivers/gpu/host1x/hw/host1x02.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 8
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x02.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1-u32max
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x02.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x02.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x02.c synchronize_syncpt_base() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 11
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x07.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x07.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x07.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x07.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x06.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x06.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x06.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x06.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x08.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x08.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x08.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x08.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x01.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 8
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x01.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1-u32max
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x01.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x01.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 8
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x01.c synchronize_syncpt_base() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 11
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x04.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 8
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x04.c channel_program_cdma() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1-u32max
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x04.c submit_setclass() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 1 offset 0
PARAM_VALUE 2 mask 0
DATA_SOURCE 0 class_id $1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x04.c submit_wait() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 78
PARAM_VALUE 2 mask 5
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock

drivers/gpu/host1x/hw/host1x04.c synchronize_syncpt_base() -> host1x_opcode_setclass()

Type Parameter Key Value
PARAM_VALUE 0 class_id 1
PARAM_VALUE 1 offset 11
PARAM_VALUE 2 mask 1
RX_PATH
TASK_NOT_RUNNING
LOCK2 &ch->cdma.lock
LOCK2 &ch->submitlock
HALF_LOCKED2 &fpriv->lock
TYPE_LOCK (struct host1x_cdma)->lock
TYPE_LOCK (struct host1x_channel)->submitlock