Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_slices_update() -> gen9_dbuf_slice_set()

Type Parameter Key Value
PARAM_VALUE 0 display 4096-ptr_max
PARAM_VALUE 0 display->cdclk.table->waveform 0,6,34952,37448,42148,42314,43604,43690,44378,46774,56246,61166,63454,65278,65534-u16max
PARAM_VALUE 0 display->drm 0,4096-ptr_max
PARAM_VALUE 0 display->info.__device_info 4096-ptr_max
PARAM_VALUE 0 display->power.domains.lock.dep_map->name 0-255
PARAM_VALUE 0 display->power.domains.lock.first_waiter->list.prev->next 5159360019465732096
PARAM_VALUE 0 display->power.domains.lock.osq.tail.counter 0-s32max
PARAM_VALUE 0 display->power.domains.lock.wait_lock.dep_map->name 0-255
PARAM_VALUE 0 display->power.domains.lock.wait_lock.owner (-1)
PARAM_VALUE 0 display->power.domains.lock.wait_lock.owner_cpu u32max
PARAM_VALUE 0 *display->bw.peakbw 0-4294967295
PARAM_VALUE 0 *display->bw.psf_bw 0-4294967295
PARAM_VALUE 0 *display->irq.pipestat_irq_mask 0-4294967295
PARAM_VALUE 1 slice 0-3
CAPPED_DATA 2 enable 1
DATA_SOURCE 0 display $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HOST_DATA 0 display->cdclk.hw.cdclk 0-16[c]
HOST_DATA 0 display->cdclk.hw.joined_mbus 0-1
HOST_DATA 0 display->cdclk.hw.voltage_level 0-31[c]
HOST_DATA 0 display->cdclk.max_cdclk_freq 1-39168016[c]
HOST_DATA 0 display->drm->mode_config.object_idr.idr_rt.xa_flags 0,4-u32max
HOST_DATA 0 display->power.chv_phy_control 0-u32max[c]
HOST_DATA 0 display->power.domains.dc_state 0-u32max
HOST_DATA 0 display->state.bxt_phy_grc 0-u32max
NO_OVERFLOW_SIMPLE 0 display->drm->num_crtcs
LOCK2 &power_domains->lock
TYPE_LOCK (struct i915_power_domains)->lock