| PARAM_VALUE |
0 |
p |
2688560332286525440 |
| PARAM_VALUE |
1 |
surf |
806485025569632256,1935010197800022016,2083860207620890624,3283436099237273600 |
| PARAM_VALUE |
1 |
surf->base_align |
0-u32max |
| PARAM_VALUE |
1 |
surf->halign |
0-72 |
| PARAM_VALUE |
2 |
prefix |
0,3448681306004553728,3823882689677201408,5407610277015969792,7023743676279713792 |
| BUF_SIZE |
0 |
p->filp |
s32min-(-2),1-s32max |
| BUF_SIZE |
0 |
p->rdev |
s32min-(-2),1-s32max |
| BUF_SIZE |
0 |
p->track |
(-1),848 |
| BUF_SIZE |
2 |
prefix |
(-1),3,6-8 |
| BUF_SIZE |
2 |
prefix |
(-1),3,6-8 |
| DATA_SOURCE |
0 |
p |
$0 |
| DATA_SOURCE |
1 |
surf |
$1 |
| DATA_SOURCE |
2 |
prefix |
$2 |
| STR_LEN |
0 |
p |
(-1),2,5-7 |
| STR_LEN |
0 |
p |
(-1),2,5-7 |
| BIT_INFO |
0 |
p->cs_flags |
0x0,0xfffffffd |
| BIT_INFO |
1 |
surf->bpe |
0x0,0x7fffffff |
| USER_DATA |
0 |
p->idx |
6-196620[c] |
| USER_DATA |
0 |
p->nchunks |
1-268435455[c][u] |
| USER_DATA |
0 |
*p->ib.ptr |
0-u32max |
| NO_OVERFLOW_SIMPLE |
0 |
p->nrelocs |
|
| USER_PTR |
0 |
p->chunks_array |
|
| USER_PTR |
0 |
p->const_ib.ptr |
|
| USER_PTR |
0 |
p->ib.ptr |
|
| LOCK2 |
|
&rdev->exclusive_lock |
|
| TYPE_LOCK |
|
(struct radeon_device)->exclusive_lock |
|
