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Documented in 1 files:

Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 4 files:

Smatch caller information:

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c dpu_encoder_phys_wb_irq_enable() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 1 irq_idx 0,5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &dpu_enc->rc_lock
HALF_LOCKED2 &dpu_enc->enc_lock
TYPE_LOCK (struct dpu_encoder_virt)->rc_lock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_control_vblank_irq() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 1 irq_idx 0,5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &phys_enc->vblank_ctl_lock
HALF_LOCKED2 &dpu_enc->rc_lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct dpu_encoder_phys)->vblank_ctl_lock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_irq_enable() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 0 dpu_kms->hw_intr->irq_lock.rlock.dep_map->name 0-255
PARAM_VALUE 0 *dpu_kms->hw_intr->cache_irq_mask 0-4294967295
PARAM_VALUE 1 irq_idx 0,5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &dpu_enc->rc_lock
HALF_LOCKED2 &dpu_enc->enc_lock
TYPE_LOCK (struct dpu_encoder_virt)->rc_lock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_control_vblank_irq() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 0 *dpu_kms->hw_intr->cache_irq_mask 0-4294967295
PARAM_VALUE 1 irq_idx 5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
LOCK2 &phys_enc->vblank_ctl_lock
HALF_LOCKED2 &dpu_enc->rc_lock
HALF_LOCKED2 &pool->lock
TYPE_LOCK (struct dpu_encoder_phys)->vblank_ctl_lock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_irq_enable() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 1 irq_idx 0,5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &dpu_enc->rc_lock
HALF_LOCKED2 &dpu_enc->enc_lock
TYPE_LOCK (struct dpu_encoder_virt)->rc_lock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_irq_enable() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 0 *dpu_kms->hw_intr->cache_irq_mask 0-4294967295
PARAM_VALUE 1 irq_idx 0,5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &dpu_enc->rc_lock
HALF_LOCKED2 &dpu_enc->enc_lock
TYPE_LOCK (struct dpu_encoder_virt)->rc_lock

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_irq_enable() -> dpu_core_irq_register_callback()

Type Parameter Key Value
PARAM_VALUE 0 *dpu_kms->hw_intr->cache_irq_mask 0-4294967295
PARAM_VALUE 1 irq_idx 5,9-32,42-48,53-54,56,63-64,387,419
PARAM_VALUE 3 irq_arg 4096-ptr_max
DATA_SOURCE 3 irq_arg $0
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2 &dpu_enc->rc_lock
HALF_LOCKED2 &dpu_enc->enc_lock
TYPE_LOCK (struct dpu_encoder_virt)->rc_lock