Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 3 files:
- drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c, line 879
- drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c, line 859
- drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c, line 866
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn35/dcn35_resource.c dcn35_dpp_create() -> dpp35_set_fgcg()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->base.caps | 8139927720979206144 |
| PARAM_VALUE | 0 | dpp->base.caps->dscl_calc_lb_num_partitions | 2103727987151736832 |
| PARAM_VALUE | 0 | dpp->base.caps->dscl_data_proc_format | 1 |
| PARAM_VALUE | 0 | dpp->base.caps->max_lb_partitions | 31 |
| PARAM_VALUE | 0 | dpp->base.ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->base.funcs | 4444220843726790656 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cm_hist_control | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cm_hist_read | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cnv_set_alpha_keyer | 8940754180848648192 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_deferred_update | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_dppclk_control | 8807426702212612096 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_full_bypass | 1891574125667397632 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_get_gamut_remap | 5985460007618125824 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_get_optimal_number_of_taps | 6596231571675275264 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_3dlut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_bias_and_scale | 6122946766709121024 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_blnd_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_cm_bias | 5628048049610002432 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_cm_dealpha | 3231198261499744256 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_gamcor_lut | 6332035748747640832 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_input_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_shaper_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_read_reg_state | 6648682024231673856 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_read_state | 3266555418275979264 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_reset | 289991515969544192 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_csc_adjustment | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_csc_default | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_degamma | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_gamut_remap | 690060690505043968 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_hdr_multiplier | 6196545892622761984 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_pre_degam | 2505855918991716352 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_scaler | 1213018339254751232 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_setup | 5961301920103157760 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_attributes | 5086891849963130880 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_matrix | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_position | 3806899027767828480 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_optional_cursor_attributes | 2054601786197250048 |
| PARAM_VALUE | 0 | dpp->base.inst | 0-3 |
| PARAM_VALUE | 0 | dpp->dispclk_r_gate_disable | 1 |
| PARAM_VALUE | 0 | dpp->tf_mask | 8220464133562814464 |
| PARAM_VALUE | 0 | dpp->tf_regs | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_DATA | 17106,17469,17832,18195,18558,18921 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_DATA_30BIT | 17107,17470,17833,18196,18559,18922 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_INDEX | 17105,17468,17831,18194,18557,18920 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_MODE | 17104,17467,17830,18193,18556,18919 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_READ_WRITE_CONTROL | 17108,17471,17834,18197,18560,18923 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_CONTROL | 16967,17330,17693,18056,18419,18782 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_CONTROL | 16970,17333,17696,18059,18422,18785 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_DATA | 16969,17332,17695,18058,18421,18784 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_INDEX | 16968,17331,17694,18057,18420,18783 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_B | 16980,17343,17706,18069,18432,18795 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_G | 16982,17345,17708,18071,18434,18797 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_R | 16984,17347,17710,18073,18436,18799 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_B | 16981,17344,17707,18070,18433,18796 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_G | 16983,17346,17709,18072,18435,18798 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_R | 16985,17348,17711,18074,18437,18800 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_0_1 | 16989,17352,17715,18078,18441,18804 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_10_11 | 16994,17357,17720,18083,18446,18809 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_12_13 | 16995,17358,17721,18084,18447,18810 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_14_15 | 16996,17359,17722,18085,18448,18811 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_16_17 | 16997,17360,17723,18086,18449,18812 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_18_19 | 16998,17361,17724,18087,18450,18813 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_20_21 | 16999,17362,17725,18088,18451,18814 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_22_23 | 17000,17363,17726,18089,18452,18815 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_24_25 | 17001,17364,17727,18090,18453,18816 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_26_27 | 17002,17365,17728,18091,18454,18817 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_28_29 | 17003,17366,17729,18092,18455,18818 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_2_3 | 16990,17353,17716,18079,18442,18805 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_30_31 | 17004,17367,17730,18093,18456,18819 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_32_33 | 17005,17368,17731,18094,18457,18820 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_4_5 | 16991,17354,17717,18080,18443,18806 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_6_7 | 16992,17355,17718,18081,18444,18807 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_8_9 | 16993,17356,17719,18082,18445,18808 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_B | 16971,17334,17697,18060,18423,18786 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_G | 16972,17335,17698,18061,18424,18787 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_R | 16973,17336,17699,18062,18425,18788 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B | 16974,17337,17700,18063,18426,18789 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G | 16975,17338,17701,18064,18427,18790 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R | 16976,17339,17702,18065,18428,18791 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_B | 17015,17378,17741,18104,18467,18830 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_G | 17017,17380,17743,18106,18469,18832 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_R | 17019,17382,17745,18108,18471,18834 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_B | 17016,17379,17742,18105,18468,18831 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_G | 17018,17381,17744,18107,18470,18833 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_R | 17020,17383,17746,18109,18472,18835 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_0_1 | 17024,17387,17750,18113,18476,18839 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_10_11 | 17029,17392,17755,18118,18481,18844 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_12_13 | 17030,17393,17756,18119,18482,18845 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_14_15 | 17031,17394,17757,18120,18483,18846 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_16_17 | 17032,17395,17758,18121,18484,18847 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_18_19 | 17033,17396,17759,18122,18485,18848 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_20_21 | 17034,17397,17760,18123,18486,18849 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_22_23 | 17035,17398,17761,18124,18487,18850 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_24_25 | 17036,17399,17762,18125,18488,18851 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_26_27 | 17037,17400,17763,18126,18489,18852 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_28_29 | 17038,17401,17764,18127,18490,18853 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_2_3 | 17025,17388,17751,18114,18477,18840 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_30_31 | 17039,17402,17765,18128,18491,18854 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_32_33 | 17040,17403,17766,18129,18492,18855 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_4_5 | 17026,17389,17752,18115,18478,18841 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_6_7 | 17027,17390,17753,18116,18479,18842 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_8_9 | 17028,17391,17754,18117,18480,18843 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_B | 17006,17369,17732,18095,18458,18821 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_G | 17007,17370,17733,18096,18459,18822 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_R | 17008,17371,17734,18097,18460,18823 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B | 17009,17372,17735,18098,18461,18824 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G | 17010,17373,17736,18099,18462,18825 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R | 17011,17374,17737,18100,18463,18826 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_CMOUT_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMA_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMA_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMB_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMB_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_DATA | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_WRITE_EN_MASK | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_REGION_14_15 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_REGION_14_15 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_RW_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_RW_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_SEQ_COLOR | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_MEM_PWR_CTRL2 | 17102,17465,17828,18191,18554,18917 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_MEM_PWR_STATUS2 | 17103,17466,17829,18192,18555,18918 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_DATA | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_WRITE_EN_MASK | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_REGION_32_33 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_REGION_32_33 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_CONTROL | 17047,17410,17773,18136,18499,18862 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_DATA | 17054,17417,17780,18143,18506,18869 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_INDEX | 17053,17416,17779,18142,18505,18868 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_WRITE_EN_MASK | 17055,17418,17781,18144,18507,18870 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_B | 17059,17422,17785,18148,18511,18874 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_G | 17060,17423,17786,18149,18512,18875 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_R | 17061,17424,17787,18150,18513,18876 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_0_1 | 17062,17425,17788,18151,18514,18877 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_10_11 | 17067,17430,17793,18156,18519,18882 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_12_13 | 17068,17431,17794,18157,18520,18883 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_14_15 | 17069,17432,17795,18158,18521,18884 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_16_17 | 17070,17433,17796,18159,18522,18885 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_18_19 | 17071,17434,17797,18160,18523,18886 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_20_21 | 17072,17435,17798,18161,18524,18887 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_22_23 | 17073,17436,17799,18162,18525,18888 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_24_25 | 17074,17437,17800,18163,18526,18889 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_26_27 | 17075,17438,17801,18164,18527,18890 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_28_29 | 17076,17439,17802,18165,18528,18891 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_2_3 | 17063,17426,17789,18152,18515,18878 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_30_31 | 17077,17440,17803,18166,18529,18892 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_32_33 | 17078,17441,17804,18167,18530,18893 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_4_5 | 17064,17427,17790,18153,18516,18879 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_6_7 | 17065,17428,17791,18154,18517,18880 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_8_9 | 17066,17429,17792,18155,18518,18881 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_B | 17056,17419,17782,18145,18508,18871 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_G | 17057,17420,17783,18146,18509,18872 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_R | 17058,17421,17784,18147,18510,18873 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_B | 17082,17445,17808,18171,18534,18897 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_G | 17083,17446,17809,18172,18535,18898 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_R | 17084,17447,17810,18173,18536,18899 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_0_1 | 17085,17448,17811,18174,18537,18900 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_10_11 | 17090,17453,17816,18179,18542,18905 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_12_13 | 17091,17454,17817,18180,18543,18906 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_14_15 | 17092,17455,17818,18181,18544,18907 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_16_17 | 17093,17456,17819,18182,18545,18908 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_18_19 | 17094,17457,17820,18183,18546,18909 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_20_21 | 17095,17458,17821,18184,18547,18910 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_22_23 | 17096,17459,17822,18185,18548,18911 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_24_25 | 17097,17460,17823,18186,18549,18912 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_26_27 | 17098,17461,17824,18187,18550,18913 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_28_29 | 17099,17462,17825,18188,18551,18914 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_2_3 | 17086,17449,17812,18175,18538,18901 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_30_31 | 17100,17463,17826,18189,18552,18915 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_32_33 | 17101,17464,17827,18190,18553,18916 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_4_5 | 17087,17450,17813,18176,18539,18902 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_6_7 | 17088,17451,17814,18177,18540,18903 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_8_9 | 17089,17452,17815,18178,18541,18904 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_B | 17079,17442,17805,18168,18531,18894 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_G | 17080,17443,17806,18169,18532,18895 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_R | 17081,17444,17807,18170,18533,18896 |
| PARAM_VALUE | 0 | dpp->tf_regs->OBUF_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->SCL_BLACK_OFFSET | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT | 0 |
| PARAM_VALUE | 0 | dpp->tf_shift | 3578583195665956864 |
| BUF_SIZE | 0 | dpp | 78272 |
| DATA_SOURCE | 0 | dpp | r _kzalloc_noprof |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn36/dcn36_resource.c dcn35_dpp_create() -> dpp35_set_fgcg()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->base.caps | 8139927720979206144 |
| PARAM_VALUE | 0 | dpp->base.caps->dscl_calc_lb_num_partitions | 2103727987151736832 |
| PARAM_VALUE | 0 | dpp->base.caps->dscl_data_proc_format | 1 |
| PARAM_VALUE | 0 | dpp->base.caps->max_lb_partitions | 31 |
| PARAM_VALUE | 0 | dpp->base.ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->base.funcs | 4444220843726790656 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cm_hist_control | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cm_hist_read | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cnv_set_alpha_keyer | 8940754180848648192 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_deferred_update | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_dppclk_control | 8807426702212612096 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_full_bypass | 1891574125667397632 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_get_gamut_remap | 5985460007618125824 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_get_optimal_number_of_taps | 6596231571675275264 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_3dlut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_bias_and_scale | 6122946766709121024 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_blnd_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_cm_bias | 5628048049610002432 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_cm_dealpha | 3231198261499744256 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_gamcor_lut | 6332035748747640832 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_input_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_shaper_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_read_reg_state | 6648682024231673856 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_read_state | 3266555418275979264 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_reset | 289991515969544192 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_csc_adjustment | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_csc_default | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_degamma | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_gamut_remap | 690060690505043968 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_hdr_multiplier | 6196545892622761984 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_pre_degam | 2505855918991716352 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_scaler | 1213018339254751232 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_setup | 5961301920103157760 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_attributes | 5086891849963130880 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_matrix | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_position | 3806899027767828480 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_optional_cursor_attributes | 2054601786197250048 |
| PARAM_VALUE | 0 | dpp->base.inst | 0-3 |
| PARAM_VALUE | 0 | dpp->dispclk_r_gate_disable | 1 |
| PARAM_VALUE | 0 | dpp->tf_mask | 2912799943146967040 |
| PARAM_VALUE | 0 | dpp->tf_regs | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_DATA | 17106,17469,17832,18195,18558,18921 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_DATA_30BIT | 17107,17470,17833,18196,18559,18922 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_INDEX | 17105,17468,17831,18194,18557,18920 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_MODE | 17104,17467,17830,18193,18556,18919 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_READ_WRITE_CONTROL | 17108,17471,17834,18197,18560,18923 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_CONTROL | 16967,17330,17693,18056,18419,18782 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_CONTROL | 16970,17333,17696,18059,18422,18785 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_DATA | 16969,17332,17695,18058,18421,18784 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_INDEX | 16968,17331,17694,18057,18420,18783 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_B | 16980,17343,17706,18069,18432,18795 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_G | 16982,17345,17708,18071,18434,18797 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_R | 16984,17347,17710,18073,18436,18799 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_B | 16981,17344,17707,18070,18433,18796 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_G | 16983,17346,17709,18072,18435,18798 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_R | 16985,17348,17711,18074,18437,18800 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_0_1 | 16989,17352,17715,18078,18441,18804 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_10_11 | 16994,17357,17720,18083,18446,18809 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_12_13 | 16995,17358,17721,18084,18447,18810 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_14_15 | 16996,17359,17722,18085,18448,18811 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_16_17 | 16997,17360,17723,18086,18449,18812 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_18_19 | 16998,17361,17724,18087,18450,18813 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_20_21 | 16999,17362,17725,18088,18451,18814 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_22_23 | 17000,17363,17726,18089,18452,18815 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_24_25 | 17001,17364,17727,18090,18453,18816 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_26_27 | 17002,17365,17728,18091,18454,18817 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_28_29 | 17003,17366,17729,18092,18455,18818 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_2_3 | 16990,17353,17716,18079,18442,18805 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_30_31 | 17004,17367,17730,18093,18456,18819 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_32_33 | 17005,17368,17731,18094,18457,18820 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_4_5 | 16991,17354,17717,18080,18443,18806 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_6_7 | 16992,17355,17718,18081,18444,18807 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_8_9 | 16993,17356,17719,18082,18445,18808 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_B | 16971,17334,17697,18060,18423,18786 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_G | 16972,17335,17698,18061,18424,18787 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_R | 16973,17336,17699,18062,18425,18788 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B | 16974,17337,17700,18063,18426,18789 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G | 16975,17338,17701,18064,18427,18790 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R | 16976,17339,17702,18065,18428,18791 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_B | 17015,17378,17741,18104,18467,18830 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_G | 17017,17380,17743,18106,18469,18832 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_R | 17019,17382,17745,18108,18471,18834 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_B | 17016,17379,17742,18105,18468,18831 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_G | 17018,17381,17744,18107,18470,18833 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_R | 17020,17383,17746,18109,18472,18835 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_0_1 | 17024,17387,17750,18113,18476,18839 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_10_11 | 17029,17392,17755,18118,18481,18844 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_12_13 | 17030,17393,17756,18119,18482,18845 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_14_15 | 17031,17394,17757,18120,18483,18846 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_16_17 | 17032,17395,17758,18121,18484,18847 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_18_19 | 17033,17396,17759,18122,18485,18848 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_20_21 | 17034,17397,17760,18123,18486,18849 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_22_23 | 17035,17398,17761,18124,18487,18850 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_24_25 | 17036,17399,17762,18125,18488,18851 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_26_27 | 17037,17400,17763,18126,18489,18852 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_28_29 | 17038,17401,17764,18127,18490,18853 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_2_3 | 17025,17388,17751,18114,18477,18840 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_30_31 | 17039,17402,17765,18128,18491,18854 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_32_33 | 17040,17403,17766,18129,18492,18855 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_4_5 | 17026,17389,17752,18115,18478,18841 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_6_7 | 17027,17390,17753,18116,18479,18842 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_8_9 | 17028,17391,17754,18117,18480,18843 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_B | 17006,17369,17732,18095,18458,18821 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_G | 17007,17370,17733,18096,18459,18822 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_R | 17008,17371,17734,18097,18460,18823 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B | 17009,17372,17735,18098,18461,18824 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G | 17010,17373,17736,18099,18462,18825 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R | 17011,17374,17737,18100,18463,18826 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_CMOUT_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMA_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMA_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMB_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMB_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_DATA | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_WRITE_EN_MASK | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_REGION_14_15 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_REGION_14_15 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_RW_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_RW_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_SEQ_COLOR | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_MEM_PWR_CTRL2 | 17102,17465,17828,18191,18554,18917 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_MEM_PWR_STATUS2 | 17103,17466,17829,18192,18555,18918 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_DATA | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_WRITE_EN_MASK | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_REGION_32_33 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_REGION_32_33 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_CONTROL | 17047,17410,17773,18136,18499,18862 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_DATA | 17054,17417,17780,18143,18506,18869 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_INDEX | 17053,17416,17779,18142,18505,18868 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_WRITE_EN_MASK | 17055,17418,17781,18144,18507,18870 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_B | 17059,17422,17785,18148,18511,18874 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_G | 17060,17423,17786,18149,18512,18875 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_R | 17061,17424,17787,18150,18513,18876 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_0_1 | 17062,17425,17788,18151,18514,18877 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_10_11 | 17067,17430,17793,18156,18519,18882 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_12_13 | 17068,17431,17794,18157,18520,18883 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_14_15 | 17069,17432,17795,18158,18521,18884 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_16_17 | 17070,17433,17796,18159,18522,18885 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_18_19 | 17071,17434,17797,18160,18523,18886 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_20_21 | 17072,17435,17798,18161,18524,18887 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_22_23 | 17073,17436,17799,18162,18525,18888 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_24_25 | 17074,17437,17800,18163,18526,18889 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_26_27 | 17075,17438,17801,18164,18527,18890 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_28_29 | 17076,17439,17802,18165,18528,18891 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_2_3 | 17063,17426,17789,18152,18515,18878 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_30_31 | 17077,17440,17803,18166,18529,18892 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_32_33 | 17078,17441,17804,18167,18530,18893 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_4_5 | 17064,17427,17790,18153,18516,18879 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_6_7 | 17065,17428,17791,18154,18517,18880 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_8_9 | 17066,17429,17792,18155,18518,18881 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_B | 17056,17419,17782,18145,18508,18871 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_G | 17057,17420,17783,18146,18509,18872 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_R | 17058,17421,17784,18147,18510,18873 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_B | 17082,17445,17808,18171,18534,18897 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_G | 17083,17446,17809,18172,18535,18898 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_R | 17084,17447,17810,18173,18536,18899 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_0_1 | 17085,17448,17811,18174,18537,18900 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_10_11 | 17090,17453,17816,18179,18542,18905 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_12_13 | 17091,17454,17817,18180,18543,18906 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_14_15 | 17092,17455,17818,18181,18544,18907 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_16_17 | 17093,17456,17819,18182,18545,18908 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_18_19 | 17094,17457,17820,18183,18546,18909 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_20_21 | 17095,17458,17821,18184,18547,18910 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_22_23 | 17096,17459,17822,18185,18548,18911 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_24_25 | 17097,17460,17823,18186,18549,18912 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_26_27 | 17098,17461,17824,18187,18550,18913 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_28_29 | 17099,17462,17825,18188,18551,18914 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_2_3 | 17086,17449,17812,18175,18538,18901 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_30_31 | 17100,17463,17826,18189,18552,18915 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_32_33 | 17101,17464,17827,18190,18553,18916 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_4_5 | 17087,17450,17813,18176,18539,18902 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_6_7 | 17088,17451,17814,18177,18540,18903 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_8_9 | 17089,17452,17815,18178,18541,18904 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_B | 17079,17442,17805,18168,18531,18894 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_G | 17080,17443,17806,18169,18532,18895 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_R | 17081,17444,17807,18170,18533,18896 |
| PARAM_VALUE | 0 | dpp->tf_regs->OBUF_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->SCL_BLACK_OFFSET | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT | 0 |
| PARAM_VALUE | 0 | dpp->tf_shift | 6297848308815761408 |
| BUF_SIZE | 0 | dpp | 78272 |
| DATA_SOURCE | 0 | dpp | r _kzalloc_noprof |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn351/dcn351_resource.c dcn35_dpp_create() -> dpp35_set_fgcg()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dpp | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->base.caps | 8139927720979206144 |
| PARAM_VALUE | 0 | dpp->base.caps->dscl_calc_lb_num_partitions | 2103727987151736832 |
| PARAM_VALUE | 0 | dpp->base.caps->dscl_data_proc_format | 1 |
| PARAM_VALUE | 0 | dpp->base.caps->max_lb_partitions | 31 |
| PARAM_VALUE | 0 | dpp->base.ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->base.funcs | 4444220843726790656 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cm_hist_control | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cm_hist_read | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_cnv_set_alpha_keyer | 8940754180848648192 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_deferred_update | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_dppclk_control | 8807426702212612096 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_full_bypass | 1891574125667397632 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_get_gamut_remap | 5985460007618125824 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_get_optimal_number_of_taps | 6596231571675275264 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_3dlut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_bias_and_scale | 6122946766709121024 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_blnd_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_cm_bias | 5628048049610002432 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_cm_dealpha | 3231198261499744256 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_gamcor_lut | 6332035748747640832 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_input_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_program_shaper_lut | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_read_reg_state | 6648682024231673856 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_read_state | 3266555418275979264 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_reset | 289991515969544192 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_csc_adjustment | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_csc_default | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_degamma | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_gamut_remap | 690060690505043968 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_hdr_multiplier | 6196545892622761984 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_pre_degam | 2505855918991716352 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_set_scaler | 1213018339254751232 |
| PARAM_VALUE | 0 | dpp->base.funcs->dpp_setup | 5961301920103157760 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_attributes | 5086891849963130880 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_matrix | 0 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_cursor_position | 3806899027767828480 |
| PARAM_VALUE | 0 | dpp->base.funcs->set_optional_cursor_attributes | 2054601786197250048 |
| PARAM_VALUE | 0 | dpp->base.inst | 0-3 |
| PARAM_VALUE | 0 | dpp->dispclk_r_gate_disable | 1 |
| PARAM_VALUE | 0 | dpp->tf_mask | 7039636474990276608 |
| PARAM_VALUE | 0 | dpp->tf_regs | 4096-ptr_max |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_DATA | 17106,17469,17832,18195,18558,18921 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_DATA_30BIT | 17107,17470,17833,18196,18559,18922 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_INDEX | 17105,17468,17831,18194,18557,18920 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_MODE | 17104,17467,17830,18193,18556,18919 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_3DLUT_READ_WRITE_CONTROL | 17108,17471,17834,18197,18560,18923 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_CONTROL | 16967,17330,17693,18056,18419,18782 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_CONTROL | 16970,17333,17696,18059,18422,18785 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_DATA | 16969,17332,17695,18058,18421,18784 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_LUT_INDEX | 16968,17331,17694,18057,18420,18783 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_B | 16980,17343,17706,18069,18432,18795 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_G | 16982,17345,17708,18071,18434,18797 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL1_R | 16984,17347,17710,18073,18436,18799 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_B | 16981,17344,17707,18070,18433,18796 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_G | 16983,17346,17709,18072,18435,18798 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_END_CNTL2_R | 16985,17348,17711,18074,18437,18800 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_0_1 | 16989,17352,17715,18078,18441,18804 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_10_11 | 16994,17357,17720,18083,18446,18809 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_12_13 | 16995,17358,17721,18084,18447,18810 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_14_15 | 16996,17359,17722,18085,18448,18811 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_16_17 | 16997,17360,17723,18086,18449,18812 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_18_19 | 16998,17361,17724,18087,18450,18813 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_20_21 | 16999,17362,17725,18088,18451,18814 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_22_23 | 17000,17363,17726,18089,18452,18815 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_24_25 | 17001,17364,17727,18090,18453,18816 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_26_27 | 17002,17365,17728,18091,18454,18817 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_28_29 | 17003,17366,17729,18092,18455,18818 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_2_3 | 16990,17353,17716,18079,18442,18805 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_30_31 | 17004,17367,17730,18093,18456,18819 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_32_33 | 17005,17368,17731,18094,18457,18820 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_4_5 | 16991,17354,17717,18080,18443,18806 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_6_7 | 16992,17355,17718,18081,18444,18807 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_REGION_8_9 | 16993,17356,17719,18082,18445,18808 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_B | 16971,17334,17697,18060,18423,18786 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_G | 16972,17335,17698,18061,18424,18787 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_CNTL_R | 16973,17336,17699,18062,18425,18788 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B | 16974,17337,17700,18063,18426,18789 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G | 16975,17338,17701,18064,18427,18790 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R | 16976,17339,17702,18065,18428,18791 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_B | 17015,17378,17741,18104,18467,18830 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_G | 17017,17380,17743,18106,18469,18832 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL1_R | 17019,17382,17745,18108,18471,18834 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_B | 17016,17379,17742,18105,18468,18831 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_G | 17018,17381,17744,18107,18470,18833 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_END_CNTL2_R | 17020,17383,17746,18109,18472,18835 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_0_1 | 17024,17387,17750,18113,18476,18839 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_10_11 | 17029,17392,17755,18118,18481,18844 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_12_13 | 17030,17393,17756,18119,18482,18845 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_14_15 | 17031,17394,17757,18120,18483,18846 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_16_17 | 17032,17395,17758,18121,18484,18847 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_18_19 | 17033,17396,17759,18122,18485,18848 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_20_21 | 17034,17397,17760,18123,18486,18849 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_22_23 | 17035,17398,17761,18124,18487,18850 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_24_25 | 17036,17399,17762,18125,18488,18851 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_26_27 | 17037,17400,17763,18126,18489,18852 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_28_29 | 17038,17401,17764,18127,18490,18853 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_2_3 | 17025,17388,17751,18114,18477,18840 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_30_31 | 17039,17402,17765,18128,18491,18854 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_32_33 | 17040,17403,17766,18129,18492,18855 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_4_5 | 17026,17389,17752,18115,18478,18841 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_6_7 | 17027,17390,17753,18116,18479,18842 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_REGION_8_9 | 17028,17391,17754,18117,18480,18843 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_B | 17006,17369,17732,18095,18458,18821 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_G | 17007,17370,17733,18096,18459,18822 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_CNTL_R | 17008,17371,17734,18097,18460,18823 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B | 17009,17372,17735,18098,18461,18824 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G | 17010,17373,17736,18099,18462,18825 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R | 17011,17374,17737,18100,18463,18826 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_BNS_VALUES_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_CMOUT_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMA_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMA_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMB_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_COMB_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_DATA | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_LUT_WRITE_EN_MASK | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_REGION_14_15 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMA_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_REGION_14_15 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_DGAM_RAMB_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_ICSC_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_RW_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_RW_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_IGAM_LUT_SEQ_COLOR | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_MEM_PWR_CTRL2 | 17102,17465,17828,18191,18554,18917 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_MEM_PWR_STATUS2 | 17103,17466,17829,18192,18555,18918 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_C11_C12 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_C33_C34 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_OCSC_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_DATA | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_INDEX | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_LUT_WRITE_EN_MASK | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_REGION_32_33 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMA_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL1_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_END_CNTL2_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_REGION_0_1 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_REGION_32_33 | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_SLOPE_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_B | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_G | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_RGAM_RAMB_START_CNTL_R | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_CONTROL | 17047,17410,17773,18136,18499,18862 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_DATA | 17054,17417,17780,18143,18506,18869 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_INDEX | 17053,17416,17779,18142,18505,18868 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_LUT_WRITE_EN_MASK | 17055,17418,17781,18144,18507,18870 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_B | 17059,17422,17785,18148,18511,18874 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_G | 17060,17423,17786,18149,18512,18875 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_END_CNTL_R | 17061,17424,17787,18150,18513,18876 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_0_1 | 17062,17425,17788,18151,18514,18877 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_10_11 | 17067,17430,17793,18156,18519,18882 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_12_13 | 17068,17431,17794,18157,18520,18883 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_14_15 | 17069,17432,17795,18158,18521,18884 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_16_17 | 17070,17433,17796,18159,18522,18885 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_18_19 | 17071,17434,17797,18160,18523,18886 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_20_21 | 17072,17435,17798,18161,18524,18887 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_22_23 | 17073,17436,17799,18162,18525,18888 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_24_25 | 17074,17437,17800,18163,18526,18889 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_26_27 | 17075,17438,17801,18164,18527,18890 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_28_29 | 17076,17439,17802,18165,18528,18891 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_2_3 | 17063,17426,17789,18152,18515,18878 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_30_31 | 17077,17440,17803,18166,18529,18892 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_32_33 | 17078,17441,17804,18167,18530,18893 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_4_5 | 17064,17427,17790,18153,18516,18879 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_6_7 | 17065,17428,17791,18154,18517,18880 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_REGION_8_9 | 17066,17429,17792,18155,18518,18881 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_B | 17056,17419,17782,18145,18508,18871 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_G | 17057,17420,17783,18146,18509,18872 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMA_START_CNTL_R | 17058,17421,17784,18147,18510,18873 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_B | 17082,17445,17808,18171,18534,18897 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_G | 17083,17446,17809,18172,18535,18898 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_END_CNTL_R | 17084,17447,17810,18173,18536,18899 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_0_1 | 17085,17448,17811,18174,18537,18900 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_10_11 | 17090,17453,17816,18179,18542,18905 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_12_13 | 17091,17454,17817,18180,18543,18906 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_14_15 | 17092,17455,17818,18181,18544,18907 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_16_17 | 17093,17456,17819,18182,18545,18908 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_18_19 | 17094,17457,17820,18183,18546,18909 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_20_21 | 17095,17458,17821,18184,18547,18910 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_22_23 | 17096,17459,17822,18185,18548,18911 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_24_25 | 17097,17460,17823,18186,18549,18912 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_26_27 | 17098,17461,17824,18187,18550,18913 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_28_29 | 17099,17462,17825,18188,18551,18914 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_2_3 | 17086,17449,17812,18175,18538,18901 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_30_31 | 17100,17463,17826,18189,18552,18915 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_32_33 | 17101,17464,17827,18190,18553,18916 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_4_5 | 17087,17450,17813,18176,18539,18902 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_6_7 | 17088,17451,17814,18177,18540,18903 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_REGION_8_9 | 17089,17452,17815,18178,18541,18904 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_B | 17079,17442,17805,18168,18531,18894 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_G | 17080,17443,17806,18169,18532,18895 |
| PARAM_VALUE | 0 | dpp->tf_regs->CM_SHAPER_RAMB_START_CNTL_R | 17081,17444,17807,18170,18533,18896 |
| PARAM_VALUE | 0 | dpp->tf_regs->OBUF_CONTROL | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->SCL_BLACK_OFFSET | 0 |
| PARAM_VALUE | 0 | dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT | 0 |
| PARAM_VALUE | 0 | dpp->tf_shift | 5166406883980189696 |
| BUF_SIZE | 0 | dpp | 78272 |
| DATA_SOURCE | 0 | dpp | r _kzalloc_noprof |
| NOCHECK_CALL |