Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 5 files:
- drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c, line 718
- drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c, line 214
- drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
- drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c, line 129
- drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c, line 129
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_dpia.c dpia_configure_link() -> dpcd_set_link_settings()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->aux_access_disabled | 0 |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->logger | 4096-ptr_max |
| PARAM_VALUE | 0 | link->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->dc->hwss.enable_dp_link_output | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->pin | 0-s64max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->pin | 0-s64max |
| PARAM_VALUE | 0 | link->dp_trace.commit_lt_trace.counts.fail | 0-s32max |
| PARAM_VALUE | 0 | link->dp_trace.commit_lt_trace.result | 0-13 |
| PARAM_VALUE | 0 | link->dpcd_caps.lttpr_caps.mode | 85,170 |
| PARAM_VALUE | 0 | link->ep_type | 1 |
| PARAM_VALUE | 0 | link->link_enc->hpd_gpio->id | s32min-s32max |
| PARAM_VALUE | 0 | link->panel_mode | 0-2 |
| PARAM_VALUE | 0 | link->phy_state.symclk_state | 1 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex->first_waiter->task->blocked_lock.owner | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_on | 0 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter | s32min-s32max |
| PARAM_VALUE | 0 | *link->dpcd_caps.lttpr_caps.aux_rd_interval | 0-255 |
| PARAM_VALUE | 1 | lt_settings | 776363108802117632 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| DATA_SOURCE | 1 | lt_settings | $3 |
| MEM_ZERO | 0 | &link->dp_trace.commit_lt_trace | |
| RX_PATH | |||
| TASK_NOT_RUNNING |
drivers/gpu/drm/amd/amdgpu/../display/dc/link/accessories/link_dp_cts.c dp_set_test_pattern() -> dpcd_set_link_settings()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.soc.dcn_downspread_percent | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.soc.downspread_percent | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.soc.dram_clock_change_latency_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.soc.sr_enter_plus_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.soc.sr_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.AverageDCCCompressionRate | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.AverageReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.AverageReadBandwidthGBytePerSecond | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.BandwidthAvailableForImmediateFlip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DCFCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DCFCLKDeepSleep | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLKDPPCLKVCOSpeed | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLKRampingMargin | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLKWithRamping | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLKWithoutRamping | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DISPCLK_calculated | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DRAMChannelWidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DRAMClockChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.DRAMSpeed | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Downspreading | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FCLKChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FabricAndDRAMBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FabricClock | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FabricDatapathToDCNDataReturn | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FinalDRAMClockChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FractionOfUrgentBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.FrameTimeForMinFullDETBufferingTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.GlobalDPPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.LastPixelOfLineExtraWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.MaxDispclkRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.MaxHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.MaxVRatioPre | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.MaxVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.MinActiveFCLKChangeLatencySupported | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.MinUrgentLatencySupportUs | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.NonUrgentLatencyTolerance | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.PartOfBurstThatFitsInROB | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.ReturnBW | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.ReturnBandwidthToDCN | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SMNLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SOCCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SREnterPlusExitTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SREnterPlusExitZ8Time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SRExitTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SRExitZ8Time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SmallestVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.StutterBurstTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.StutterEfficiency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.StutterEfficiencyNotIncludingVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.StutterEnterPlusExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.StutterExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.StutterPeriod | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.SwathWidthYCriticalPlane | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.TCalc | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.TFinalxFill | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.TotalDataReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.TotalRowReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.TslvChk | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.USRRetrainingLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentExtraLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentLatencyPixelDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentLatencyPixelMixedWithVMData | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentLatencyVMDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentRoundTripAndOutOfOrderLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.UrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.VBlankTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.VStartupMargin | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.DRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.FCLKChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.StutterExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.USRRetrainingWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.UrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.WritebackUrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Watermark.Z8StutterExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackDISPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackDRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackMaxHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackMaxVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackMinHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackMinVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.WritebackUrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCBusTransportTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCFillBWOverhead | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCRemoteSurfaceFlipDelay | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCTSlvVreadyOffset | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCTSlvVupdateOffset | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCTSlvVupdateWidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.XFCXBUFLatencyTolerance | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Z8StutterEfficiency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Z8StutterEfficiencyBestCase | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Z8StutterEnterPlusExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.Z8StutterExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.soc.dcn_downspread_percent | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.soc.downspread_percent | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.soc.dram_clock_change_latency_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.soc.sr_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_dlg_sys_param.mem_trip_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_dlg_sys_param.t_extra_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_dlg_sys_param.t_sr_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_dlg_sys_param.t_urg_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_dlg_sys_param.total_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.clks_cfg.dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.clks_cfg.dispclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.clks_cfg.dppclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.clks_cfg.refclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.clks_cfg.socclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.dout.output_bpp | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.dout.wb.wb_hratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.dout.wb.wb_vratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->current_state->res_ctx.temp_pipe.pipe_dlg_param.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->current_test_pattern | 1-25 |
| PARAM_VALUE | 0 | link->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ddc->ctx->driver_context->dm.dpia_aux_lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->pending_test_pattern | 33 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex->first_waiter->task->blocked_lock.owner | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->prev | 0,5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->magic | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_on | 0 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | link->test_pattern_enabled | 1 |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_clock->pin->en | 0-4294967295 |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_clock->pin->id | s32min-s32max |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_clock->pin->mode | s32min-s32max |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_clock->pin->opened | 0-1 |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_data->pin->en | 0-4294967295 |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_data->pin->id | s32min-s32max |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_data->pin->mode | s32min-s32max |
| PARAM_VALUE | 0 | *link->ddc->ddc_pin->pin_data->pin->opened | 0-1 |
| PARAM_VALUE | 1 | lt_settings | 4096-ptr_max |
| BUF_SIZE | 0 | link->dc | (-1),3059296 |
| BUF_SIZE | 0 | link->priv | (-1),9272 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| DATA_SOURCE | 1 | lt_settings | $3 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_128b_132b.c dp_perform_128b_132b_link_training() -> dpcd_set_link_settings()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->chip_caps | 2-u16max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.soc.dram_clock_change_latency_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.soc.sr_enter_plus_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.soc.sr_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.AverageDCCCompressionRate | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.AverageReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.AverageReadBandwidthGBytePerSecond | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DCFCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKDPPCLKVCOSpeed | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKRampingMargin | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKWithRampingRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKWithoutRampingRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLK_calculated | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMChannelWidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMClockChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMSpeed | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Downspreading | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FCLKChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FabricAndDRAMBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FabricClock | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FabricDatapathToDCNDataReturn | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FinalDRAMClockChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FrameTimeForMinFullDETBufferingTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.GlobalDPPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.LinesToFinishSwathTransferStutterCriticalPlane | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxDispclkRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxVRatioPre | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MinActiveDRAMClockChangeLatencySupported | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MinActiveFCLKChangeLatencySupported | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MinUrgentLatencySupportUs | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.NonUrgentLatencyTolerance | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.ReturnBandwidthToDCN | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SMNLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SOCCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SREnterPlusExitTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SREnterPlusExitZ8Time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SRExitTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SRExitZ8Time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SmallestVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterEfficiency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterEfficiencyNotIncludingVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterEnterPlusExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterPeriod | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SwathWidthYCriticalPlane | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TCalc | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TFinalxFill | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TotalDataReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TotalRowReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TslvChk | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.USRRetrainingLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentExtraLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyAdjustmentFabricClockComponent | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyAdjustmentFabricClockReference | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyPixelDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyPixelMixedWithVMData | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyVMDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentRoundTripAndOutOfOrderLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.VBlankTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.VStartupMargin | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackDRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMaxHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMaxVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMinHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMinVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackUrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCBusTransportTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCFillBWOverhead | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCRemoteSurfaceFlipDelay | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCTSlvVreadyOffset | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCTSlvVupdateOffset | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCTSlvVupdateWidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCXBUFLatencyTolerance | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiencyBestCase | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiencyNotIncludingVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiencyNotIncludingVBlankBestCase | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEnterPlusExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.soc.dram_clock_change_latency_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.soc.sr_enter_plus_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.soc.sr_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.total_dcn_read_bw_with_flip_no_urgent_burst | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->dc->debug.legacy_dp2_lt | 0 |
| PARAM_VALUE | 0 | link->dc->hwss.enable_dp_link_output | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->pin | 0-s64max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->pin | 0-s64max |
| PARAM_VALUE | 0 | link->dpcd_caps.lttpr_caps.mode | 85,170 |
| PARAM_VALUE | 0 | link->phy_state.symclk_state | 1 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex->first_waiter->task->blocked_lock.owner | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_on | (-1)-0 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter | s32min-s32max |
| PARAM_VALUE | 0 | *link->ctx->dc->scratch.pipes_to_unlock_first | 0-1 |
| PARAM_VALUE | 0 | *link->dpcd_caps.edp_supported_link_rates | 0-4294967295 |
| PARAM_VALUE | 0 | *link->dpcd_caps.lttpr_caps.aux_rd_interval | 0-255 |
| PARAM_VALUE | 1 | lt_settings | 18841051748196352 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| DATA_SOURCE | 1 | lt_settings | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c perform_fixed_vs_pe_nontransparent_training_sequence() -> dpcd_set_link_settings()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->chip_caps | 2-u16max |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->dc->hwss.enable_dp_link_output | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->pin | 0-s64max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->pin | 0-s64max |
| PARAM_VALUE | 0 | link->dpcd_caps.lttpr_caps.mode | 85,170 |
| PARAM_VALUE | 0 | link->ext_enc_id.id | 0 |
| PARAM_VALUE | 0 | link->phy_state.symclk_state | 1 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter | s32min-s32max |
| PARAM_VALUE | 0 | *link->dpcd_caps.lttpr_caps.aux_rd_interval | 0-255 |
| PARAM_VALUE | 1 | lt_settings | 18841051748196352 |
| PARAM_VALUE | 1 | lt_settings->cr_pattern_time | 16000-u16max |
| PARAM_VALUE | 1 | lt_settings->lttpr_mode | 3 |
| DATA_SOURCE | 0 | link | $0 |
| DATA_SOURCE | 1 | lt_settings | $2 |
| FUZZY_MAX | 1 | lt_settings->cr_pattern_time | 16000 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_8b_10b.c dp_perform_8b_10b_link_training() -> dpcd_set_link_settings()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->chip_caps | 2-u16max |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.soc.dram_clock_change_latency_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.soc.sr_enter_plus_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.soc.sr_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.AverageDCCCompressionRate | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.AverageReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.AverageReadBandwidthGBytePerSecond | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DCFCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKDPPCLKVCOSpeed | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKRampingMargin | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKWithRampingRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLKWithoutRampingRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DISPCLK_calculated | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMChannelWidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMClockChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DRAMSpeed | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Downspreading | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FCLKChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FabricAndDRAMBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FabricClock | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FabricDatapathToDCNDataReturn | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FinalDRAMClockChangeLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.FrameTimeForMinFullDETBufferingTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.GlobalDPPCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.LinesToFinishSwathTransferStutterCriticalPlane | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxDispclkRoundedToDFSGranularity | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxVRatioPre | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MaxVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MinActiveDRAMClockChangeLatencySupported | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MinActiveFCLKChangeLatencySupported | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.MinUrgentLatencySupportUs | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.NonUrgentLatencyTolerance | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.ReturnBandwidthToDCN | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SMNLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SOCCLK | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SREnterPlusExitTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SREnterPlusExitZ8Time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SRExitTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SRExitZ8Time | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SmallestVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterEfficiency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterEfficiencyNotIncludingVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterEnterPlusExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.StutterPeriod | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.SwathWidthYCriticalPlane | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TCalc | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TFinalxFill | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TotalDataReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TotalRowReadBandwidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.TslvChk | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.USRRetrainingLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentExtraLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyAdjustmentFabricClockComponent | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyAdjustmentFabricClockReference | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyPixelDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyPixelMixedWithVMData | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentLatencyVMDataOnly | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentRoundTripAndOutOfOrderLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.UrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.VBlankTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.VStartupMargin | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackDRAMClockChangeWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackLatency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMaxHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMaxVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMinHSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackMinVSCLRatio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.WritebackUrgentWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCBusTransportTime | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCFillBWOverhead | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCRemoteSurfaceFlipDelay | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCTSlvVreadyOffset | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCTSlvVupdateOffset | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCTSlvVupdateWidth | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.XFCXBUFLatencyTolerance | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiency | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiencyBestCase | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiencyNotIncludingVBlank | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEfficiencyNotIncludingVBlankBestCase | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterEnterPlusExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.Z8StutterExitWatermark | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.soc.dram_clock_change_latency_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.soc.sr_enter_plus_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.soc.sr_exit_time_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.total_dcn_read_bw_with_flip_no_urgent_burst | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | link->dc->hwss.enable_dp_link_output | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->pin | 0-s64max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->pin | 0-s64max |
| PARAM_VALUE | 0 | link->dpcd_caps.lttpr_caps.mode | 85,170 |
| PARAM_VALUE | 0 | link->phy_state.symclk_state | 1 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex->first_waiter->task->blocked_lock.owner | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_on | (-1)-0 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter | s32min-s32max |
| PARAM_VALUE | 0 | *link->ctx->dc->scratch.pipes_to_unlock_first | 0-1 |
| PARAM_VALUE | 0 | *link->dpcd_caps.edp_supported_link_rates | 0-4294967295 |
| PARAM_VALUE | 0 | *link->dpcd_caps.lttpr_caps.aux_rd_interval | 0-255 |
| PARAM_VALUE | 1 | lt_settings | 18841051748196352,7843724607067631616 |
| PARAM_VALUE | 1 | lt_settings->lttpr_early_tps2 | 0 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| DATA_SOURCE | 1 | lt_settings | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_8b_10b.c set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence() -> dpcd_set_link_settings()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->chip_caps | 2-u16max |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->dc->hwss.enable_dp_link_output | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ddc->ctx->driver_context->dm.dpia_aux_lock.osq.tail.counter | 0-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_clock->pin | 0-s64max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->id | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->ddc->ddc_pin->pin_data->pin | 0-s64max |
| PARAM_VALUE | 0 | link->dpcd_caps.lttpr_caps.mode | 85,170 |
| PARAM_VALUE | 0 | link->phy_state.symclk_state | 1 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex->first_waiter->task->blocked_lock.owner | (-4611686018427387904)-4611686018427387903 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->list.prev->next | 5159360019465732096 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner | (-1) |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->blocked_lock.owner_cpu | 4294967295 |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.first_waiter->task->usage.refs.counter | s32min-s32max |
| PARAM_VALUE | 0 | link->priv->dm_dp_aux.aux.hw_mutex.osq.tail.counter | s32min-s32max |
| PARAM_VALUE | 0 | *link->dpcd_caps.lttpr_caps.aux_rd_interval | 0-255 |
| PARAM_VALUE | 1 | lt_settings | 18841051748196352,7843724607067631616 |
| PARAM_VALUE | 1 | lt_settings->lttpr_early_tps2 | 1 |
| DATA_SOURCE | 0 | link | $0 |
| DATA_SOURCE | 1 | lt_settings | $2 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |