Defined in 1 files as a prototype:
Defined in 1 files as a member:
Defined in 1 files as a function:
Referenced in 2 files:
- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
- drivers/gpu/drm/amd/display/dc/link/link_factory.c
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_edp_power_control() -> (struct link_service)->dp_trace_get_edp_poweron_timestamp()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->link_srv | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk | 0,4,4096-ptr_max |
| PARAM_VALUE | 0 | link->link_enc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->link_enc->funcs->is_dig_enabled | 0,835999835047198720,2505374968371208192,3400303375799660544,6908382666642669568 |
| PARAM_VALUE | 0 | link->link_enc->hpd_gpio->pin->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->panel_cntl | 4096-ptr_max |
| PARAM_VALUE | 0 | link->panel_cntl->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | *link->dpcd_caps.edp_supported_link_rates | 0-4294967295 |
| BUF_SIZE | 0 | link | (-1),1616 |
| BUF_SIZE | 0 | link | (-1),1616 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL | 0-u32max |
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 | 0-u32max |
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL | 0-u32max |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_edp_power_control() -> (struct link_service)->dp_trace_get_edp_poweron_timestamp()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->link_srv | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk | 0,4,4096-ptr_max |
| PARAM_VALUE | 0 | link->link_enc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->link_enc->funcs->is_dig_enabled | 0,835999835047198720,2505374968371208192,3400303375799660544,6908382666642669568 |
| PARAM_VALUE | 0 | link->link_enc->hpd_gpio->pin->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->panel_cntl | 4096-ptr_max |
| PARAM_VALUE | 0 | link->panel_cntl->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | *link->dpcd_caps.edp_supported_link_rates | 0-4294967295 |
| BUF_SIZE | 0 | link | (-1),1616 |
| BUF_SIZE | 0 | link | (-1),1616 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL | 0-u32max |
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 | 0-u32max |
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL | 0-u32max |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_edp_power_control() -> (struct link_service)->dp_trace_get_edp_poweron_timestamp()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | link | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPChroma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->dml.vba.DPPCLKUsingSingleDPPLuma | -inf-1.797693e+308 |
| PARAM_VALUE | 0 | link->ctx->dc->link_srv | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk | 0,4,4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc_bios | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc_bios->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | link->ctx->dc_bios->funcs->transmitter_control | 4096-ptr_max |
| PARAM_VALUE | 0 | link->link_enc | 4096-ptr_max |
| PARAM_VALUE | 0 | link->link_enc->funcs->is_dig_enabled | 0,835999835047198720,2505374968371208192,3400303375799660544,6908382666642669568 |
| PARAM_VALUE | 0 | link->link_enc->hpd_gpio->pin->mode | s32min-s32max |
| PARAM_VALUE | 0 | link->panel_cntl | 4096-ptr_max |
| PARAM_VALUE | 0 | link->panel_cntl->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | *link->dpcd_caps.edp_supported_link_rates | 0-4294967295 |
| BUF_SIZE | 0 | link | (-1),1616 |
| BUF_SIZE | 0 | link | (-1),1616 |
| CAPPED_DATA | 0 | link | 1 |
| DATA_SOURCE | 0 | link | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL | 0-u32max |
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 | 0-u32max |
| HOST_DATA | 0 | link->panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL | 0-u32max |