dml21_program_dc_pipe identifier - Linux source code next-20260811

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linux

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FIXME
- FIXME
  - next-20260811

Defined in 1 files as a prototype:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h, line 40 (as a prototype)

Defined in 1 files as a function:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c, line 213 (as a function)

Referenced in 1 files:

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
- line 114
- line 117

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/dml21_wrapper_fpu.c dml21_calculate_rq_and_dlg_params() -> dml21_program_dc_pipe()

Type	Parameter	Key	Value
PARAM_VALUE	0	dml_ctx	4096-ptr_max
PARAM_VALUE	0	dml_ctx->architecture	1
PARAM_VALUE	0	dml_ctx->config.callbacks.get_otg_master_for_stream	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.callbacks.get_stream_from_id	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.callbacks.get_stream_status	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.skip_hw_state_mapping	0
PARAM_VALUE	0	dml_ctx->v21.display_config.gpuvm_max_page_table_levels	1-u32max
PARAM_VALUE	0	dml_ctx->v21.display_config.minimize_det_reallocation	1
PARAM_VALUE	0	dml_ctx->v21.display_config.num_planes	1-s32max
PARAM_VALUE	0	dml_ctx->v21.display_config.num_streams	1-s32max
PARAM_VALUE	0	dml_ctx->v21.display_config.overrides.all_streams_blanked	1
PARAM_VALUE	0	dml_ctx->v21.display_config.overrides.enable_subvp_implicit_pmo	1
PARAM_VALUE	0	dml_ctx->v21.display_config.overrides.hw.force_unbounded_requesting.enable	1
PARAM_VALUE	0	dml_ctx->v21.mode_programming.dml2_instance	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.mode_programming.dml2_instance->funcs.build_mode_programming	0,7150732188596219904
PARAM_VALUE	0	dml_ctx->v21.mode_programming.programming	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.mode_programming.programming->plane_programming	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.mode_programming.programming->stream_programming	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.deepsleep_dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.mem_trip_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_extra_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_sr_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_urg_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.total_flip_bw	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.wb.wb_hratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.wb.wb_vratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_chroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_luma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.pipe_dlg_param.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid	1
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id	0-4294967295
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid	1
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id	0-4294967295
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid	0-1
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id	0-4294967295
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid	0-1
PARAM_VALUE	1	context	4096-ptr_max
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.dppclk_khz	(-2147483631)-s32max
PARAM_VALUE	3	pln_prog	4096-ptr_max
PARAM_VALUE	3	pln_prog->num_dpps_required	1-u32max
PARAM_VALUE	3	pln_prog->plane_descriptor	1-u64max
PARAM_VALUE	4	stream_prog->stream_descriptor->writeback.active_writebacks_per_stream	1-3
DATA_SOURCE	0	dml_ctx	$3
DATA_SOURCE	1	context	$1
FUZZY_MAX	4	stream_prog->stream_descriptor->writeback.active_writebacks_per_stream	1
MEM_ZERO	0	&dml_ctx->v21.display_config
MEM_ZERO	0	&dml_ctx->v21.dml_to_dc_pipe_mapping
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/dml21_wrapper_fpu.c dml21_calculate_rq_and_dlg_params() -> dml21_program_dc_pipe()

Type	Parameter	Key	Value
PARAM_VALUE	0	dml_ctx	4096-ptr_max
PARAM_VALUE	0	dml_ctx->architecture	1
PARAM_VALUE	0	dml_ctx->config.callbacks.get_odm_slice_index	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.callbacks.get_opp_head	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.callbacks.get_otg_master_for_stream	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.callbacks.get_stream_from_id	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.callbacks.get_stream_status	4096-ptr_max
PARAM_VALUE	0	dml_ctx->config.skip_hw_state_mapping	0
PARAM_VALUE	0	dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.display_config.gpuvm_max_page_table_levels	1-u32max
PARAM_VALUE	0	dml_ctx->v21.display_config.minimize_det_reallocation	1
PARAM_VALUE	0	dml_ctx->v21.display_config.num_planes	1-s32max
PARAM_VALUE	0	dml_ctx->v21.display_config.num_streams	1-s32max
PARAM_VALUE	0	dml_ctx->v21.display_config.overrides.all_streams_blanked	1
PARAM_VALUE	0	dml_ctx->v21.display_config.overrides.enable_subvp_implicit_pmo	1
PARAM_VALUE	0	dml_ctx->v21.display_config.overrides.hw.force_unbounded_requesting.enable	1
PARAM_VALUE	0	dml_ctx->v21.mode_programming.dml2_instance	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.mode_programming.dml2_instance->funcs.build_mode_programming	0,7150732188596219904
PARAM_VALUE	0	dml_ctx->v21.mode_programming.programming	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.mode_programming.programming->plane_programming	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.mode_programming.programming->stream_programming	4096-ptr_max
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.deepsleep_dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.mem_trip_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_extra_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_sr_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.t_urg_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_dlg_sys_param.total_flip_bw	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.clks_cfg.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.wb.wb_hratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.dout.wb.wb_vratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_chroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_luma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	dml_ctx->v21.scratch.temp_pipe.pipe_dlg_param.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid	1
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id	0-4294967295
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid	1
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id	0-4294967295
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid	0-1
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id	0-4294967295
PARAM_VALUE	0	*dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid	0-1
PARAM_VALUE	1	context	4096-ptr_max
PARAM_VALUE	1	context->bw_ctx.bw.dcn.clk.dppclk_khz	(-2147483631)-s32max
PARAM_VALUE	2	pipe_ctx	1-u64max
PARAM_VALUE	3	pln_prog	4096-ptr_max
PARAM_VALUE	3	pln_prog->num_dpps_required	1-u32max
PARAM_VALUE	3	pln_prog->phantom_plane.valid	1
PARAM_VALUE	3	pln_prog->plane_descriptor	1-u64max
PARAM_VALUE	3	pln_prog->surface_size_mall_bytes	0
PARAM_VALUE	4	stream_prog	4096-ptr_max
PARAM_VALUE	4	stream_prog->stream_descriptor->writeback.active_writebacks_per_stream	1-3
DATA_SOURCE	0	dml_ctx	$3
DATA_SOURCE	1	context	$1
FUZZY_MAX	4	stream_prog->stream_descriptor->writeback.active_writebacks_per_stream	1
MEM_ZERO	0	&dml_ctx->v21.display_config
MEM_ZERO	0	&dml_ctx->v21.dml_to_dc_pipe_mapping
PREEMPT_ADD
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL