| PARAM_VALUE |
0 |
ts |
4096-ptr_max |
| DATA_SOURCE |
0 |
ts |
$0 |
| NOCHECK_CALL |
|
|
|
| HOST_DATA |
0 |
ts->base.flashboot |
0-1 |
| HOST_DATA |
0 |
ts->base.fw_blksize |
0-u32max |
| HOST_DATA |
0 |
ts->base.msi_enabled |
0-255 |
| HOST_DATA |
0 |
ts->base.pcie_irq_count |
0-u32max |
| HOST_DATA |
0 |
ts->base.reclaim_tq.count.counter |
s32min-s32max |
| HOST_DATA |
0 |
ts->base.reclaim_tq.data |
0-u64max |
| HOST_DATA |
0 |
ts->base.reclaim_tq.state |
0-u64max |
| HOST_DATA |
0 |
ts->base.reclaim_tq.use_callback |
0-1 |
| HOST_DATA |
0 |
ts->base.rx_bd_num |
0-u16max |
| HOST_DATA |
0 |
ts->base.rx_bd_r_index |
0-u32max |
| HOST_DATA |
0 |
ts->base.rx_bd_w_index |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.direction |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.irq_work.data.counter |
s64min-s64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.rx_packet_count |
0-u64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.done |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.magic |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.owner_cpu |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.raw_lock.locked |
0-255 |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.raw_lock.locked_pending |
0-u16max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.raw_lock.pending |
0-255 |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.raw_lock.tail |
0-u16max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_completion.wait.lock.raw_lock.val.counter |
s32min-s32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_packet_count |
0-u64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.tx_timeout_count |
0-u64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_in.waiting_for_ack |
0-255 |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.direction |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.irq_work.data.counter |
s64min-s64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.rx_packet_count |
0-u64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.done |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.magic |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.owner_cpu |
0-u32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.raw_lock.locked |
0-255 |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.raw_lock.locked_pending |
0-u16max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.raw_lock.pending |
0-255 |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.raw_lock.tail |
0-u16max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_completion.wait.lock.raw_lock.val.counter |
s32min-s32max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_packet_count |
0-u64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.tx_timeout_count |
0-u64max |
| HOST_DATA |
0 |
ts->base.shm_ipc_ep_out.waiting_for_ack |
0-255 |
| HOST_DATA |
0 |
ts->base.tx_bd_num |
0-u16max |
| HOST_DATA |
0 |
ts->base.tx_bd_r_index |
0-u32max |
| HOST_DATA |
0 |
ts->base.tx_bd_w_index |
0-u32max |
| HOST_DATA |
0 |
ts->base.tx_done_count |
0-u32max |
| HOST_DATA |
0 |
ts->base.tx_full_count |
0-u32max |
| HOST_DATA |
0 |
ts->base.tx_reclaim_done |
0-u32max |
| HOST_DATA |
0 |
ts->base.tx_reclaim_req |
0-u32max |
| HOST_DATA |
0 |
ts->base.tx_stopped |
0-255 |
| HOST_DATA |
0 |
ts->dma_msi_dummy |
0-u64max |
| HOST_DATA |
0 |
ts->dma_msi_imwr |
0-u32max |
| HOST_DATA |
0 |
ts->rx_pkt_count |
0-u64max |
| HOST_DATA |
0 |
*ts |
s64min-s64max |
| HALF_LOCKED2 |
|
&pool->lock |
|